Process for the formation of a spatial chip arrangement and...

Details Process for the formation of a spatial chip arrangement and... Process for the formation of a spatial chip arrangement and...

2006-08-08

2006-08-08

Graybill, David E. (Department: 2822)

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

C438S109000, C438S117000, C438S723000, C257SE25006, C257SE25013, C257SE25027

Reexamination Certificate

active

07087442

ABSTRACT:
Process for the formation of a spatial chip arrangement having several chips (32, 36, 37, 38, 39) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces (33) to assigned conducting paths (23) of a conducting-path structure (24, 25) arranged on at least one carrier substrate (21, 22) by the chips being arranged transverse to the longitudinal extent of the carrier substrate.

REFERENCES:
patent: 3105869 (1963-10-01), Branch et al.
patent: 4770640 (1988-09-01), Walter
patent: 4833568 (1989-05-01), Berhold
patent: 4862249 (1989-08-01), Carlson
patent: 4922378 (1990-05-01), Malhi et al.
patent: 4953005 (1990-08-01), Carlson et al.
patent: 4983533 (1991-01-01), Go
patent: 5006925 (1991-04-01), Bregman et al.
patent: 5016138 (1991-05-01), Woodman
patent: 5031072 (1991-07-01), Malhi et al.
patent: 5151559 (1992-09-01), Conru et al.
patent: 5224023 (1993-06-01), Smith et al.
patent: 5239447 (1993-08-01), Cotues et al.
patent: 5241450 (1993-08-01), Bernhardt et al.
patent: 5247423 (1993-09-01), Lin et al.
patent: 5279029 (1994-01-01), Burns
patent: 5285571 (1994-02-01), Gorczyca et al.
patent: 5313096 (1994-05-01), Eide
patent: 5327327 (1994-07-01), Frew et al.
patent: 5343075 (1994-08-01), Nishino
patent: 5345205 (1994-09-01), Kornrumpf
patent: 5397916 (1995-03-01), Normington
patent: 5425493 (1995-06-01), Interrante et al.
patent: 5448511 (1995-09-01), Paurus et al.
patent: 5466634 (1995-11-01), Beilstein et al.
patent: 5475920 (1995-12-01), Burns et al.
patent: 5514907 (1996-05-01), Moshayedi
patent: 5517754 (1996-05-01), Beilstein et al.
patent: 5566051 (1996-10-01), Burns
patent: 5567654 (1996-10-01), Beilstein et al.
patent: 5588205 (1996-12-01), Roane
patent: 5592364 (1997-01-01), Roane
patent: 5602420 (1997-02-01), Ogata et al.
patent: 5604377 (1997-02-01), Palagonia
patent: 5646446 (1997-07-01), Nicewarner, Jr. et al.
patent: 5648684 (1997-07-01), Bertin et al.
patent: 5653381 (1997-08-01), Azdasht
patent: 5656856 (1997-08-01), Kweon
patent: 5754405 (1998-05-01), Derouiche
patent: 5790380 (1998-08-01), Frankeny
patent: 5793116 (1998-08-01), Rinne et al.
patent: 5828031 (1998-10-01), Pattanaik
patent: 5854534 (1998-12-01), Beilin et al.
patent: 5963793 (1999-10-01), Rinne et al.
patent: 6121676 (2000-09-01), Solberg
patent: 6188127 (2001-02-01), Senba et al.
patent: 6208521 (2001-03-01), Nakatsuka
patent: 6227437 (2001-05-01), Razon et al.
patent: 6838060 (2005-01-01), Chapus et al.
patent: 0 521 735 (1993-01-01), None
patent: 0 527 044 (1993-02-01), None
patent: 0 810 661 (1997-12-01), None
patent: 3-64088 (1991-03-01), None
patent: 03171646 (1991-07-01), None
patent: 6-13727 (1994-01-01), None
patent: WO 82/04161 (1982-11-01), None
IBM Technical Disclosure Bulletin, vol. 38, No. 01, pp. 69-70 (Jan. 1995).
IBM Technical Disclosure Bulletin, vol. 38, No. 06, p. 1 (Jun. 1995).

Affiliated with

Also associated with

Rating

Process for the formation of a spatial chip arrangement and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for the formation of a spatial chip arrangement and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for the formation of a spatial chip arrangement and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3645356