Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-06-17
2000-05-02
Booth, Richard
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438265, 438525, 438302, 438526, H01L 21336
Patent
active
060571918
ABSTRACT:
A process for the manufacturing of integrated circuits provides for forming contacts between a conductive material layer and first doped regions of a semiconductor substrate in a self-aligned manner to edges of an insulating material layer which defines active areas of the integrated circuit wherein the doped regions are formed, and second doped regions of the same conductivity type as the first doped regions under the first doped regions, the second doped regions extending partially under the edges of the insulating material layer to prevent short-circuits between the conductive material layer and the semiconductor substrate. The second doped regions are formed by means of implantation of dopants along directions slanted with respect to an orthogonal direction to a surface of the semiconductor substrate at angles and with an energy sufficiently high to make the dopants penetrate in the semiconductor material deeper than the first doped regions and under the edges of the insulating material layer.
REFERENCES:
patent: 4107719 (1978-08-01), Graul et al.
patent: 4357178 (1982-11-01), Bergeron et al.
patent: 4535532 (1985-08-01), Lancaster
patent: 5376566 (1994-12-01), Gonzalez
patent: 5378641 (1995-01-01), Cheffings
patent: 5426063 (1995-06-01), Kaneko et al.
patent: 5459085 (1995-10-01), Pasen et al.
patent: 5482881 (1996-01-01), Chen et al.
patent: 5593907 (1997-01-01), Anjum et al.
patent: 5624859 (1997-04-01), Liu et al.
patent: 5670392 (1997-09-01), Ferla et al.
Ghandhi, S.K., VLSI Fabrication Principles, Silicon and Gallium Arsenide, pp. 731-734, 1994.
Wolf, S., Silicon Processing for the VLSI Era, vol. 1-Process Technology, 1986.
European Search Report from European Patent Application 96830362.8, filed Jun. 26, 1996.
Patent Abstract of Japan, vol. 017, No. 334 (E-1387), Jun. 24, 1993 & JP 05 041385, to Kiyoto.
Patent Abstract of Japan, vol. 96, No. 7, Jul. 31, 1996 & JP 08 078681 to Kunihiro.
Patent Abstract of Japan, vol. 13, No. 490 (E-841), Nov. 7, 1989 & JP 07 147327, to Takashi.
Patent Abstract of Japan, vol. 95, No. 009, Oct. 31, 1955 & JP 07 147327, to Akio.
Booth Richard
Galanthay Theodore E.
Hack Jonathan
Morris James H.
SGS--Thomson Microelectronics S.r.l.
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