Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-29
2001-11-20
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S258000, C438S981000
Reexamination Certificate
active
06319780
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the fabrication of integrated circuits and, more particularly, to a process for forming an integrated circuit comprising low voltage MOS transistors, EPROM cells, and high voltage MOS transistors. The low voltage MOS transistors include gate electrodes separated from a substrate by a first dielectric material. The high voltage MOS transistors include gate electrodes separated from the substrate by a second dielectric material. The EPROM cells include floating gate electrodes separated from the substrate by a third dielectric material, and includes corresponding control electrodes separated from the floating gate electrodes by the second dielectric material.
BACKGROUND OF THE INVENTION
In the design of integrated circuit devices intended for the processing of digital signals, such as microprocessors, for example, it is sometimes necessary to include an electrically programmable non-volatile memory cell and corresponding decoding circuits in the same integrated circuit. These electrically programmable non-volatile memory cells are known as electrically programmable read only memories EPROMS.
This requirement gives rise to considerable problems in manufacture, and primarily because of the following reason. The processing circuits, or logic circuits for short, are made using low voltage technology. Low voltage technology uses processes for forming devices, particularly MOS transistors, capable of withstanding relative low voltages within a range of 1 to 3 V. Low voltage throughout the application will be indicated by the symbol LV.
In contrast, the decoding circuits of the memories require devices, essentially MOS transistors, capable of operating at relatively high voltages within a range of 7 to 10 V. High voltage throughout the application will be indicated by the symbol HV. This means that the gate dielectrics of the HV devices must have physical characteristics and/or thicknesses which are different from those used in the LV devices. Therefore, the HV devices require special operations for their formation and definition.
In addition, the gate dielectrics of EPROM cells require a thickness which is different from that of the gate dielectrics of the LV devices and the HV devices. The gate dielectrics of EPROM cells also requires specific characteristics to ensure the permanence of the stored data over time.
A prior art process for forming the different types of devices in a single integrated circuit includes the combination of the three specific processes for forming the three types of devices. In other words, this process requires a number of masking operations close to the sum of the masking operations of the three specific processes. However, a process of this kind has a high cost due to both the large number of operations required, and the resulting low yield. The production yield decreases with an increase in a number of operations in the process.
Producing HV circuits together with LV circuits without making use of specific processes for HV devices can be accomplished using a known circuit arrangement in which two or more LV devices, connected in a cascode configuration, are used. However, this approach can be applied advantageously only when the number of HV devices is small. Otherwise, because each HV device is formed from at least two LV devices, the supplementary area required becomes unacceptably large. Moreover, this does not help with the formation of the memory cells. All the specific operations for producing memory cells have to be added to the process in any case.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a process for forming low voltage circuits, high voltage circuits and EPROM memory cells of the one time programmable OTP type within a single integrated circuit by using a small number of operations in addition to those normally used for forming low voltage circuits. This achieves a production yield very close to that which can be achieved with a process designed for forming logic circuits with transistors of the low voltage type.
A process is provided for forming an integrated circuit comprising at least one low voltage MOS transistor, at least one high voltage MOS transistor, and at least one EPROM cell. The process comprises defining on a silicon substrate at least one low voltage MOS transistor area, at least one high voltage MOS transistor area, and at least one EPROM cell area. Body regions are then preferably formed for the at least one low voltage MOS transistor area, for the at least one high voltage MOS transistor area, and for the at least one EPROM cell area.
The process preferably further includes forming a first dielectric layer on the silicon substrate, forming a first conducting layer on the first dielectric layer, removing the first conducting layer from the at least one EPROM cell area for forming a floating gate, and forming source and drain regions in the body region for the at least one EPROM cell area. The first conducting layer and the first dielectric layer are preferably removed from the at least one high voltage MOS transistor area.
The process preferably further includes forming a second dielectric layer on the silicon substrate for the at least one high voltage MOS transistor area, on the floating gate and the first dielectric layer for the at least one EPROM cell area, and on the first conducting layer for the at least one low voltage MOS transistor area. The second dielectric layer, the first conducting layer and the first dielectric layer are preferably removed from the at least one low voltage MOS transistor area.
A third dielectric layer is preferably formed on the silicon substrate for the at least one low voltage MOS transistor area, and a second conducting layer is formed on the third dielectric layer, and on the second dielectric layer for the at least one EPROM cell area and the at least one high voltage MOS transistor area. The second conducting layer is preferbly selectively removed to form a gate for the at least one low voltage MOS transistor, to form a gate for the at least one high voltage MOS transistor, and to form a control gate for the at least one EPROM cell. Source and drain regions are then preferably formed in the body region for the low voltage MOS transistor area for the at least one low voltage MOS transistor, and in the body region for the high voltage MOS transistor area for the at least one high voltage MOS transistor.
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Patent Abstracts of Japan vol. 018, No. 266 (E-1551), May 20, 1994, & JP 06 045 614 A (Nec Corp), Feb. 18, 1994.
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Crivelli Barbara
Palumbo Elisabetta
Peschiaroli Daniela
Zatelli Nicola
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Chaudhari Chandra
Jorgenson Lisa K.
STMicroelectronics S.r.l.
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