Process for simultaneous formation of silicide-based self-aligne

Details Process for simultaneous formation of silicide-based self-aligne Process for simultaneous formation of silicide-based self-aligne

1996-08-01

1997-09-16

Quach, T. N.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438649, H01L 21283, H01L 21335

Patent

active

056680651

ABSTRACT:
A process for simultaneously forming a self-aligned contact, a local interconnect and a self-aligned silicide in a semiconductor device. An oxide layer is deposited over a gate structure, a source region and a drain region formed on a substrate of the semiconductor device. The gate structure may be a multi-layer structure including a polysilicon gate, a silicon nitride layer and a tungsten silicide layer. The oxide layer deposited over the gate, source and drain is etched to define portions of the oxide layer which will form contact areas of a self-aligned contact and a local interconnect of the semiconductor device. An amorphous silicon layer is then deposited over the etched oxide layer to a thickness selected such that substantially the entire thickness of remaining portions of the amorphous silicon layer will be consumed during a subsequent silicidation reaction. The amorphous silicon layer is etched to remove portions of the amorphous silicon layer which will not be used to form a portion of the self-aligned contact and local interconnect, as well as remaining non-contact area portions of the underlying oxide layer. A metal layer is deposited over the etched amorphous silicon layer, and an annealing process is applied such that the etched amorphous silicon layer and the deposited metal layer react to provide a silicide layer which forms a portion of the self-aligned contact and the local interconnect. The annealing process also causes the deposited metal layer to react with exposed source and/or drain regions to thereby form a self-aligned silicide.

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