Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-10-03
2004-08-03
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S624000, C438S626000, C438S678000
Reexamination Certificate
active
06770536
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a semiconductor device and, more specifically, to a semiconductor device having an insulating layer formed on a III-V semiconductor substrate by Atomic Layer Deposition and a method of manufacture thereof.
BACKGROUND OF THE INVENTION
High speed active device applications in the telecommunication industry based on III-V semiconductors offer a number of advantages over devices based on Silicon semiconductors. The broad application of III-V semiconductors in such devices has been problematic, however. It has been difficult, for example, to incorporate GaAs into metal oxide semiconductor field effect transistors (MOSFETs). Specifically, it has proven difficult to form an insulating layer of oxide or high dielectric constant material on GaAs semiconductor substrates and still obtain a functional device.
It is thought that the Fermi level of the GaAs semiconductor substrate at an interface between the GaAs and the insulating layer is substantially pinned, arising from a poor-quality interface characteristic of III-V surfaces, resulting in an MOSFET that has inadequate performance characteristics for functional device applications. Inadequate performance characteristics associated with pinning include insensitivity in a change in the MOSFET's drain current in response to a bias voltage applied to the gate for a given input voltage. This may manifest, for example, as a low transconductance or by an inability of the drain current to change as the bias voltage changes from positive or negative or vice versa.
The use of III-V semiconductors has therefore been limited largely to devices, such as metal semiconductor field effect transistors (MESFETs), that do not have an insulating layer on the III-V semiconductor. High leakage currents remain a drawback of such devices, because there is an inherently low energy barrier (about 0.7 eV) between the III-V semiconductor and the overlying conducting layer. The use of such III-V based MESFETs is also problematic in high voltage applications, such as base stations of cell phone systems where it is desirable to amplify a weak RF signal. In such applications, a high positive voltage (e.g., in excess of about 2 V) can not be applied to the gate. If a high positive voltage is applied then a current may run between the gate and the drain or source along the surface of the III-V semiconductor, thereby causing a breakdown of the MESFET.
Accordingly, what is needed in the art is a semiconductor device and method of manufacturing thereof that does not exhibit the limitations of the prior art.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a method of manufacturing a semiconductor device. The method includes providing a III-V semiconductor substrate and depositing by Atomic Layer Deposition, an insulating layer on the III-V semiconductor substrate. Another embodiment of the present invention is an active device comprising the above-described III-V semiconductor substrate and insulating layer on the substrate.
Still another embodiment is directed to a transistor, comprising a III-V semiconductor substrate, a gate located on the III-V semiconductor substrate, a source and a drain formed in or on said III-V semiconductor substrate, and the above-described insulating layer. The insulating layer is deposited on the III-V semiconductor substrate, by Atomic Layer Deposition, between at least one of the source or drain regions and the gate. Moreover, the insulating layer is capable of acting as a passivation layer to hinder surface currents when a bias voltage is applied to the gate.
The foregoing has outlined preferred and alternative features of the present invention so that those of ordinary skill in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the scope of the invention.
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Wilk Glen David
Ye Peide
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