Process for removing high stressed film using LF or HF bias...

Details Process for removing high stressed film using LF or HF bias... Process for removing high stressed film using LF or HF bias...

2007-01-23

2009-06-02

Chen, Kin-Chan (Department: 1792)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C216S068000, C156S345420

Reexamination Certificate

active

07541289

ABSTRACT:
A method of fabricating multilayer interconnect structures on a semiconductor wafer begins by roughening the interior surface of a metal lid to a surface roughness in excess of SA 2000 with a reentrant surface profile, and installing the metal lid as the ceiling of a plasma clean reactor chamber having a wafer pedestal facing the interior surface of the ceiling.

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