Process for reliable ultrathin oxynitride formation

Details Process for reliable ultrathin oxynitride formation Process for reliable ultrathin oxynitride formation

1998-09-08

2001-06-12

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S770000, C438S778000, C438S786000

Reexamination Certificate

active

06245689

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to processes for the formation of ultra-thin dielectric layers for use as gate or tunnel oxides employed in integrated circuits.
BACKGROUND OF THE INVENTION
The trend in integrated circuits is toward higher performance, higher speed, and lower cost. Correspondingly, device dimensions and feature sizes are shrinking for all types of integrated circuit technology. This trend necessitates the use of ultra-thin dielectrics in the fabrication of such devices as Metal-Oxide-Semiconductor (MOS) transistors and floating gate memory elements.
MOS transistors are comprised of highly doped source and drain regions in a silicon substrate, and a conducting gate electrode is situated between the source and drain but separated from the substrate by a thin gate dielectric layer. When an appropriate voltage is applied to the gate electrode, a conducting channel is created between the source and drain. Shorter channels, shallower source and drain junctions, and thinner gate dielectrics are critical to achieving smaller and faster MOS devices.
Certain Electrically Erasable Programmable Read-Only Memory (EEPROM) elements utilize a two layer polysilicon structure comprising an electrically disconnected polysilicon gate electrode, referred to as “floating gate”, and a second control transistor gate above the floating gate and more removed from the substrate. The floating gate, which retains electrical charge for a long time period unless altered by an external energy source, is charged or discharged by quantum mechanical tunneling of electrons through very thin dielectrics known as “tunnel oxides”. The threshold voltage of the control transistor differs for the charged and uncharged states of the floating gate.
Presently, ultra thin dielectrics less than 100 Angstroms thick, usually of high quality SiO
2
, are utilized as MOS gate dielectrics (commonly called gate oxides), and as tunnel oxides in floating gate EEPROM memory elements. Reliability and reproducibility of these ultra-thin oxides can be adversely affected by many factors including lack of thickness control, poor interface structure, high defect density, and impurity diffusion through the oxides. These factors can seriously degrade device performance.
Diffusion of impurities, particularly boron, through thin oxides is a major problem in processing technology. In Complementary MOS (CMOS) technology, many front end processing steps such as polysilicon gate deposition can be performed simultaneously for the NMOS and PMOS devices of CMOS circuits; however, the dopant implantation steps are performed separately, since different dopants are required. Arsenic and phosphorous, donor-type materials which provide free electrons as charge carriers, are most often used to dope the gate and source/drain regions of the NMOS devices. Boron, an acceptor-type material which provides free holes as charge carriers, is the most often used dopant for PMOS devices. Boron from the doped polysilicon gate has a much higher diffusion rate through the gate oxide layer than do arsenic or phosphorus, and can cause severe degradation of PMOS device characteristics. A concentration of charged boron ions within the gate oxide degrades the insulating characteristics of the oxide, causing gate oxide rupture at sufficiently high concentration. Additionally, boron charge within the gate oxide results in a shift of the transistor threshold voltage V
T
. The magnitude of this shift is a function of the concentration of diffused boron ions times the depth of their penetration into the oxide. For ultra-thin gate oxides, boron can diffuse completely through the gate oxide into the underlying substrate, causing even more severe threshold shift problems. Similar problems with boron diffusion are evidenced for the very thin tunnel oxides used in floating gate memory elements of EEPROMS. The resulting degradation in oxide breakdown characteristics lowers the number of possible program erase cycles.
Poor interface structure between a Si substrate and an SiO
2
layer results largely from strain caused by lattice mismatch between Si and SiO
2
. One consequence of this is the formation of interface states during high electric field stress or during exposure to high energy radiation such as x-rays. These interface states cause degradation of transistor turn-on characteristics.
Incorporation of nitrogen into the thin oxide layer has been shown to inhibit boron diffusion and to improve the Si—SiO
2
interfacial structure. Specifically, a nitrogen concentration profile having a double peaked structure with a peak of nitrogen at the Si—SiO
2
interface and a peak at the SiO
2
surface adjacent the polysilicon gate in MOSFET's, and having a low nitrogen concentration therebetween, has been shown to effectively impede boron diffusion from the doped polysilicon gate and to maintain oxide integrity. Additionally, incorporation of nitrogen at the Si—SiO
2
interface has been shown to relax the interfacial strain and improve the immunity of the oxides to interface state generation under high field stress.
Several methods for forming a nitrided oxide layer have been used. The first of these is referred to as the Nitrided Oxide (NO) method, which is described by M. Moslehi et al in
J Electrochem Soc: Solid State Science and Technology,
Vol 132, No. 9, September 1985, pp 2189-2197, which is hereby incorporated by reference. This method comprises growing a thin thermal oxide on the Si substrate which is then annealed in an ammonia (NH
3
) atmosphere to incorporate nitrogen into the oxide. Furnace anneal was initially utilized, but most recently, Rapid Thermal Anneal (RTA) has been used as an alternative. Using the NO method, peaks in nitrogen concentration are seen at the Si—SiO
2
interface, hereafter referred to as the “interface”, and at the SiO
2
surface adjacent the polysilicon gate in MOSFET's, hereafter referred to as the “oxide surface”. The nitrogen concentration within the oxide film increases monotonically with nitridation time. Thin oxides fabricated using the NO method exhibit improved resistance to boron penetration, as well as improved Si—SiO
2
interfacial characteristics and low defect densities. However, decomposition of NH
3
during the nitridation process also results in incorporation of hydrogen into the SiO
2
layer. Si—H bonds and Si—OH bonds form, causing a large increase in electron and hole trapping and a high density of fixed charges, which result in threshold voltage instability for MOSFET's and degradation of breakdown endurance for MOSFET's and EEPROMs.
A second method, known as the reOxidized Nitrided Oxide (ONO) method, is described by T. Hori et al in
IEEE Transactions on Electron Devices,
Vol. 36, No. 2 February 1989, pp 340-350, also hereby incorporated by reference. The ONO method adds an additional high-temperature (800-1200° C.) oxidation step after the ammonia nitidation of the NO method. The hydrogen incorporated into the oxide layer during the ammonia nitridation is reduced by the oxygen present during the subsequent oxidation step, and diffuses out at the high oxidation temperature. As reoxidation proceeds, the hydrogen concentration in the film is found to decrease monotonically, with the rate of decrease depending on the reoxidation temperature and on the nitrogen peak concentration. The hydrogen concentration approaches a minimum value approximately equal to the hydrogen levels found in thermally grown oxide. A more heavily nitrided surface layer is thought to act as a higher barrier for oxygen diffusion, making the reoxidation process slower. The reduction in hydrogen concentration is shown to proportionately reduce the electron charge trapping evidenced in the nitrided oxides.
A disadvantage of the ONO method is the relatively narrow process window for achievement of optimum oxide quality. Over-reoxidation has been shown to actually degrade oxide electrical qualities. A further disadvantage of the NO and ONO processes is the high level of nitrogen in the bulk of the oxide. The bulk n

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