Process for reducing hydrogen contamination in dielectric...

Details Process for reducing hydrogen contamination in dielectric... Process for reducing hydrogen contamination in dielectric...

2003-05-05

2004-05-25

Guerrero, Maria (Department: 2822)

Semiconductor device manufacturing: process

Radiation or energy treatment modifying properties of...

C438S798000, C438S791000, C438S471000, C438S473000, C438S474000

Reexamination Certificate

active

06740605

ABSTRACT:

TECHNICAL FIELD
The present invention relates to semiconductor devices and the fabrication thereof and, more particularly, to a process for reducing hydrogen contamination in dielectric materials in memory devices.
BACKGROUND ART
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in memory device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. Many memory devices utilize a charge trapping dielectric material, such as an oxide-nitride-oxide (ONO) structure. For example, one memory device that utilizes the ONO structure is a silicon-oxide-nitride-oxide-silicon (SONOS) type cell. Another memory device that utilizes the ONO structure is a floating gate FLASH memory device, in which the ONO structure is formed over the floating gate, typically a polysilicon floating gate.
During the programming of charge trapping dielectric charge storage devices, electrical charge is transferred from a substrate to the charge trapping dielectric charge storage layer in the device, e.g., the nitride layer in a SONOS device. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to become trapped in the charge trapping dielectric material. This jump is known as hot carrier injection (HCI), the hot carriers being electrons. Charges are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the charge trapping dielectric layer near the source region. Because parts of the charge trapping dielectric layer are not electrically conductive, the charges introduced into these parts of the charge trapping dielectric material tend to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous charge trapping dielectric layer.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within a charge trapping dielectric layer and have designed memory circuits that utilize two or more regions of stored charge within the charge storage layer. This type of non-volatile memory device is known as a dual-bit, two-bit or multi-bit memory cell. In dual-bit memory cells, a left bit and a right bit are stored in physically different areas of the silicon nitride layer, in left and right regions of each memory cell, respectively. The above-described programming methods are used to enable the two bits to be programmed and read simultaneously. Each of the two bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions. In addition, multi-bit memory cells recently have been developed, in which more than two bits can be stored in separate regions of a single charge storage layer of the memory cell. As used herein, the term “multi-bit” refers to both dual-bit and higher-bit memory cells, unless otherwise specifically stated.
Various aspects of the memory cell, such as the charge storage layer, spacers, and etch stop layers (ESL), have conventionally been made from a material such as silicon nitride. Such silicon nitride aspects have conventionally been deposited by plasma enhanced chemical vapor deposition (PECVD). The charge storage layer and spacers are usually deposited by LPCVD and ESL is usually by PECVD. PECVD tends to contain more hydrogen but even LPCVD contains some hydrogen and causes problems. For example, the conventionally employed PECVD method can impart from about 10 to about 30 atomic percent hydrogen into the deposited silicon nitride, whether the nitride is a charge storage layer, a spacer, or an ESL. Thus, there is a need to reduce hydrogen content in either instance.
As device dimensions continue to be scaled down, the hydrogen content of nitrides can present a problem to devices such as charge trapping dielectric memory devices. Although not to be bound by theory, it is hypothesized that excess hydrogen conventionally found in the nitrides can migrate into the dielectric layers separating the charge storage layer from the substrate and the control gate electrode. Specifically, excess hydrogen is thought to migrate into the bottom dielectric layer, or into the top dielectric layer. The presence of this additional hydrogen in the bottom dielectric layer and/or top dielectric layer is thought to result in changes in the barrier height of these layers, and thus to affect performance of the charge storage dielectric memory device.
While Si—H bonds are of particular concern, any hydrogen bonds, such as N—H bonds in memory cell nitrides can theoretically affect the performance of charge storage dielectric memory devices. Thus, the hydrogen content of memory cell nitrides presents a problem to proper functioning of the ever-smaller devices.
Accordingly, advances in the fabrication and treatment of memory cell nitrides to eliminate hydrogen are needed. Thus, the present invention provides a process for removing hydrogen from memory cell nitrides.
DISCLOSURE OF THE INVENTION
According to the present invention, there is provided a process for removing hydrogen contamination from a semiconductor device. In one embodiment, the method includes steps of forming at least one dielectric layer, wherein the dielectric layer comprises dielectric-hydrogen bonds; irradiating the dielectric layer with ultraviolet radiation sufficient to break at least a portion of the dielectric-hydrogen bonds; and annealing the dielectric layer in an atmosphere comprising at least one gas having at least one atom capable of forming dielectric-atom bonds, whereby at least a portion of dielectric-hydrogen bonds are replaced with dielectric-atom bonds.
Also according to the present invention, there is provided a process for fabricating a semiconductor device. In one embodiment, the method includes providing a semiconductor substrate; forming an ONO material over the semiconductor substrate; forming a gate electrode layer over the ONO material; forming a dielectric spacer adjacent to the stacked gate and a dielectric etch stop layer over the stacked gate and protective spacer such that at least one of the dielectric spacer and dielectric etch stop layer comprises dielectric-hydrogen bonds; irradiating at least one of the dielectric spacer and the dielectric etch stop layer with ultraviolet radiation sufficient to break at least a portion of the dielectric-hydrogen bonds; and annealing at least one of the spacer and the etch stop layer in an atmosphere comprising at least one gas having at least one atom capable of forming dielectric-atom bonds, whereby at least a portion of dielectric-hydrogen bonds are replaced with dielectric-atom bonds.
In further accordance with the present invention, there is provided a process for fabricating a semiconductor device. The process includes providing a semiconductor substrate; forming an oxide layer over the semiconductor substrate; forming a nitride layer over the oxide layer, the oxide lay

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