Process for protecting array top oxide

Details Process for protecting array top oxide Process for protecting array top oxide

2000-09-27

2003-01-21

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S244000, C438S245000, C438S386000, C438S387000, C438S388000

Reexamination Certificate

active

06509226

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to integrated circuit (IC) memory devices and, more particularly, to a process for protecting the array top oxide in vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic random access memory (DRAM) arrays.
BACKGROUND DESCRIPTION
In the present process for memory cell fabrication in vertical MOSFET DRAM arrays, removal of the ES (etch stop) nitride liner from the array results in thinning of the underlying top oxide which is intended to provide insulation between the silicon substrate and the word lines to be formed subsequently. Thinning of the top oxide results in a higher than desired incidence of word line to substrate shorts and/or leakage. Furthermore, thinning of the top oxide may result in the formation of divots in the array gate conductor (GC) polycrystalline silicon (polysilicon) in the top portion of the deep trench, due to gate stack overetch. Divots in the array GC polysilicon which are deeper than the bit line diffusion (XA) junction result in non-functional array MOSFETs due to gate underlap.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a protective etch stop layer under the etch supports (ES) nitride liner.
According to the invention, processing of a DRAM device containing vertical MOSFET arrays proceeds in a normal fashion through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide which provides array top insulation. Then a thin polysilicon or amorphous silicon layer is deposited (new layer) over the planarized surface and the normal second pad nitride (active area (AA) pad nitride) and tetraethyl orthosilicate (TEOS) stack is deposited. The AA mask is used to open the pad layer to the silicon surface, and standard shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is perfomed, the isolation trenches are filled with high density plasma (HDP) oxide and then planarized to the top surface of the AA pad nitride (the TEOS layer overlying t he second pad nitride having been polished off). Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying TTO. The standard etch support (ES) nitride liner is then deposited, and the process continues with the patterning of the ES mask which opens the support areas. The ES nitride, thin polysilicon layer and TTO are etched from the exposed areas. Next, a sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Then, using the etch array (EA) mask, the support gate polysilicon is opened in t he array. The ES nitride is removed selective to the underlying silicon layer, protecting the TTO. The gate stack is deposited and patterned and the process continues to completion.


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patent: 6229173 (2001-05-01), Gruening et al.
patent: 6258659 (2001-07-01), Gruening et al.

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