Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-04-07
1998-07-14
Dutton, Brian
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438257, H01L 218238, H01L 21336
Patent
active
057803285
ABSTRACT:
When the source and drain regions (an n.sup.- type semiconductor region and an n.sup.+ type semiconductor region) of a complementary MISFET and a p-type semiconductor region for use as a punch-through stopper are formed in a p-type well in a substrate having a p- and an n-type well, p-type impurities for the punch-through stopper are suppressed from being supplied to the feeding portion (an n.sup.+ type semiconductor region) of the n-type well.
REFERENCES:
patent: 5188976 (1993-02-01), Kume et al.
patent: 5407853 (1995-04-01), Komori et al.
Asayama Kyoichiro
Fukuda Kazushi
Haga Satoru
Hashimoto Naotaka
Hoshino Yutaka
Dutton Brian
Hitachi , Ltd.
Hitachi ULSI Engineering Co., Ltd.
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