Process for producing semiconductor article using graded...

Details Process for producing semiconductor article using graded... Process for producing semiconductor article using graded...

2001-08-10

2003-06-03

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S933000

Reexamination Certificate

active

06573126

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a production of a general substrate of relaxed Si
1−x
Ge
x
-on-insulator (SGOI) for various electronics or optoelectronics applications, and the production of monocrystalline III-V or II-VI material-on-insulator substrate.
Relaxed Si
1−x
Ge
x
-on-insulator (SGOI) is a very promising technology as it combines the a benefits of two advanced technologies: the conventional SOI technology and the disruptive SiGe technology. The SOI configuration offers various advantages associated with the insulating substrate, namely reduced parasitic capacitances, improved isolation, reduced short-channel-effect, etc. High mobility strained-Si, strained-Si
1−x
Ge
x
or strained-Ge MOS devices can be made on SGOI substrates.
Other III-V optoelectronic devices can also be integrated into the SGOI substrate by matching the lattice constants of III-V materials and the relaxed Si
1−x
Ge
x
. For example a GaAs layer can be grown on Si
1−x
Ge
x
-on-insulator where x is equal or close to 1. SGOI may serve as an ultimate platform for high speed, low power electronic and optoelectronic applications.
SGOI has been fabricated by several methods in the prior art. In one method, the separation by implantation of oxygen (SIMOX) technology is used to produce SGOI. High dose oxygen implant was used to bury high concentrations of oxygen in a Si
1−x
Ge
x
layer, which was then converted into a buried oxide (BOX) layer upon annealing at high temperature (for example, 1350° C.). See, for example, Mizuno et al. IEEE Electron Device Letters, Vol. 21, No. 5, pp. 230-232, 2000 and Ishilawa et al. Applied Physics Letters, Vol. 75, No. 7, pp. 983-985, 1999. One of the main drawbacks is the quality of the resulting Si
1−x
Ge
x
film and BOX. In addition, Ge segregation during high temperature anneal also limits the maximum Ge composition to a low value.
U.S. Pat. Nos. 5,461,243 and 5,759,898 describe a second method, in which a conventional silicon-on-insulator (SOI) substrate was used as a compliant substrate. In the process, an initially strained Si
1−x
Ge
x
layer was deposited on a thin SOI substrate. Upon an anneal treatment, the strain was transferred to the thin silicon film underneath, resulting in relaxation of the top Si
1−x
Ge
x
film. The final structure is relaxed-SiGe/strained-Si/insulator, which is not an ideal SGOI structure. The silicon layer in the structure is unnecessary, and may complicate or undermine the performance of devices built on it. For example, it may form a parasitic back channel on this strained-Si, or may confine unwanted electrons due to the band gap offset between the strained-Si and SiGe layer.
U.S. Pat. Nos. 5,906,951 and 6,059,895 describe the formation of a similar SGOI structure: strained-layer(s)/relaxed-SiGe/Si/insulator structure. The structure was produced by wafer bonding and etch back process using a P
++
layer as an etch stop. The presence of the silicon layer in the above structure may be for the purpose of facilitating Si-insulator wafer bonding, but is unnecessary for ideal SGOI substrates. Again, the silicon layer may also complicate or undermine the performance of devices built on it. For example, it may form a parasitic back channel on this strained-Si, or may confine unwanted electrons due to the band gap offset between the strained-Si and SiGe layer. Moreover, the etch stop of P
++
in the above structure is not practical when the first graded Si
1−y
Ge
y
layer described in the patents has a y value of larger than 0.2. Experiments from research shows Si
1−y
Ge
y
with y larger than 0.2 is a very good etch stop for both KOH and TMAH, as described in a published PCT application WO 99/53539. Therefore, the KOH will not be able to remove the first graded Si
1−y
Ge
y
layer and the second relaxed SiGe layer as described in the patents.
Other attempts include re-crystallization of an amorphous Si
1−x
Ge
x
layer deposited on the top of SOI (silicon-on-insulator) substrate, which is again not an ideal SGOI substrate and the silicon layer is unnecessary, and may complicate or undermine the performance of devices built on it. Note Yeo et al. IEEE Electron Device Letters, Vol. 21, No. 4, pp. 161-163, 2000. The relaxation of the resultant SiGe film and quality of the resulting structure are main concerns.
From the above, there is a need for a simple technique for relaxed SGOI substrate production, a need for a technique for production of high quality SGOI and other III-V material-on-insulator, and a need for a technique for wide range of material transfer.
SUMMARY OF THE INVENTION
According to the invention, there is provided an improved technique for production of wide range of high quality material is provided. In particular, the production of relaxed Si
1−x
Ge
x
-on-insulator (SGOI) substrate or relaxed III-V or II-VI material-on-insulator, such as GaAs-on-insulator, is described. High quality monocrystalline relaxed SiGe layer, relaxed Ge layer, or other relaxed III-V material layer is grown on a silicon substrate using a graded Si
1−x
Ge
x
epitaxial growth technique. A thin film of the layer is transferred into an oxidized handle wafer by wafer bonding and wafer splitting using hydrogen ion implantation. The invention makes use of the graded Si
1−x
Ge
x
buffer structure, resulting in a simplified and improved process.
The invention also provides a method allowing a wide range of device materials to be integrated into the inexpensive silicon substrate. For example, it allows production of Si
1−x
Ge
x
-on-insulator with wide range of Ge concentration, and allows production of many III-V or II-VI materials on insulator like GaAs, AlAs, ZnSe and InGaP. The use of graded Si
1−x
Ge
x
buffer in the invention allows high quality materials with limited dislocation defects to be produced and transferred. In one example, SGOI is produced using a SiGe structure in which a region in the graded buffer can act as a natural etch stop.
The invention provides a process and method for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si
1−x
Ge
x
(x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si
1−y
Ge
y
layer, a thin strained Si
1−z
Ge
z
layer and another relaxed Si
1−y
Ge
y
layer. Hydrogen ions are then introduced into the strained Si
z
Ge
z
layer. The relaxed Si
1−y
Ge
y
layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, whereby the second relaxed Si
1−y
Ge
y
layer remains on said second substrate.
In another exemplary embodiment, a graded Si
1−x
Ge
x
is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, whereby the upper portion of relaxed GaAs layer remains on said second substrate.


REFERENCES:
patent: 4010045 (1977-03-01), Ruehrwein
patent: 5013681 (1991-05-01), Godbey et al.
patent: 5166084 (1992-11-01), Pfiester
patent: 5202284 (1993-04-01), Kamins et al.
patent: 5207864 (1993-05-01), Bhat et al.
patent: 5208182 (1993-05-01), Narayan et al.
patent: 5212110 (1993-05-01), Pfiester et al.
patent: 5221413 (1993-06-01), Brasen et al.
patent: 5285086 (1994-02-01), Fitzgerald
patent: 5310451 (1994-05-01), Tejwani et al.
patent: 5346848 (1994-09-01), Grupen-Shemansky et al.
patent: 5374564 (1994-12-01), Bruel
patent: 5413679 (1995-05-01), Godbey
patent: 5442205 (1995-08-01), Brasen et al.
patent: 5461243 (1995-10-01), Ek et al.
patent: 5462883 (1995-10-01),

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