Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-07
2002-06-18
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S257000
Reexamination Certificate
active
06406961
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a process for producing a memory, and more particularly to a process for producing a flash memory which involves in self alignment of a floating gate structure with a field oxide structure.
BACKGROUND OF THE INVENTION
Among various types of non-volatile memories, an electrically erasable programmable read only memory is more and more popular, and especially a flash memory is developing significantly.
Please refer to FIGS.
1
A~
1
H which schematically show a conventional process for producing a flash memory. First of all, a pad oxide layer
101
, a silicon nitride layer
102
and a photoresist layer
103
are sequentially formed on a silicon substrate
100
, as shown in FIG.
1
A. Using a first photo-masking and lithography procedure to pattern the silicon nitride layer
102
to obtain a mask
12
, as shown in FIG.
1
B. With the shield of the mask
12
, a field oxide (FOX) structure
104
are grown, as shown in FIG.
1
C. The silicon nitride mask
12
and the pad oxide
101
thereunder are then removed to expose the substrate
100
to complete the definition of an active area
105
, as shown in FIG.
1
D. Over the substrate with the active area
105
, a tunnel oxide layer
106
, a doped polysilicon layer
107
, another silicon nitride layer
108
and another photoresist
109
are sequentially formed, as shown in FIG.
1
E. Using a second photo-masking and lithography procedure to pattern the silicon nitride layer
108
to obtain a mask
18
, as shown in FIG.
1
F. With the shield of the mask
18
, an oxide structure
110
and a floating gate structure
111
are defined, and then the mask
18
is removed, as shown in FIG.
1
G. Subsequently, another doped polysilicon layer is applied to the resulting substrate to define a control gate structure
112
, as shown in
FIG. 1H. A
top plane view of the resulting structure is schematically shown in
FIG. 2
wherein the cross-sectional view of
FIG. 1H
is taken along the A-A′ line of FIG.
2
. For further illustration, a cross-sectional view taken along the B-B′ line of
FIG. 2
is shown in
FIG. 3
which also shows source/drain regions
13
defined later.
It is understood from the above description, the formation of the field oxide structure and the floating gate structure are performed by respective masking and lithography procedures. Therefore, mis-alignment may occur between the field oxide structure and the floating gate structure so as to result in a poor yield. In order to solve this problem, it is necessary to remain a clearance, e.g. about 0.1~0.15 microns for each side, between the field oxide structure and the floating gate structure for tolerance. As known, such a clearance has an adverse effect on the integration of the device. On the other hand, the relatively large coupling effect between the floating gate and the control gate requires a relatively high voltage to perform a programming or erasing operation, thereby increasing the difficulty in performing these operations.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a process for producing a memory structure without mis-alignment between the field oxide structure and the floating gate structure.
Another object of the present invention is to provide a process for producing a memory structure with a reduced coupling effect between the floating gate and the control gate.
According to a first aspect of the present invention, a process for producing a memory structure, includes steps of: providing a substrate; sequentially applying a tunnel dielectric layer and a first conductive layer onto the substrate; creating a trench in the first conductive layer; applying a first insulating layer onto the first conductive layer, which fills the trench; creating an implanting window in the first insulating layer; defining a source region on the substrate through the implanting window; applying a masking layer onto the substrate with the first conductive layer, the first insulating layer and the implanting window, and etching the masking layer to form a patterned mask; reacting a portion of the first conductive layer without the shield of the patterned mask to form a second insulating layer, and removing the patterned mask, and an unreacted portion of the first conductive layer exposed from the shield of the patterned mask, thereby forming a floating gate structure; forming an insulating spacer structure around the floating gate structure; applying a second conductive layer onto the substrate with the second insulating layer and the insulating spacer structure, and etching the second conductive layer to form a control gate structure; and defining a drain region on the substrate.
In an embodiment, the substrate is a silicon substrate, the tunnel dielectric layer is a silicon oxide layer, the first conductive layer is a doped polysilicon layer, the masking layer is a silicon nitride layer, the insulating spacer structure is formed of silicon nitride, and the second conductive layer is a doped polysilicon layer.
Preferably, the first insulating layer is applied onto the first conductive layer by chemical vapor deposition.
Preferably, the first insulating layer is further treated by a planarization procedure, e.g. a chemical mechanical polishing procedure.
Preferably, the second insulating layer is formed by a thermal oxidation procedure.
According to another aspect of the present invention, a process for producing a memory structure, includes steps of: providing a substrate; applying a tunnel dielectric layer onto the substrate; applying a first conductive layer onto the tunnel dielectric layer, which is trenched to include alternate trench portion and conductive portion; filling the trench portion with a first insulating material to form a first insulating structure beside the conductive portion; removing a portion of the first insulating structure to create an implanting window through which ion-implantation is performed to define a source region; masking the conductive portion according to a predetermined pattern, and transforming the un-masked conductive portion into a top-insulated conductive portion; removing the masked conductive portion to isolate the top-insulated conductive portion to form a floating gate structure; forming an insulating spacer structure around the floating gate structure; applying a second conductive layer over the floating gate structure, which is patterned to form a control gate structure; and defining a drain region on the substrate.
Preferably, the un-masked conductive portion is transformed into a top-insulated conductive portion by a thermal oxidation procedure.
According to a third aspect of the present invention, a process for producing a memory structure, includes steps of: providing a substrate; applying a tunnel dielectric layer onto the substrate; forming a floating gate layer on the tunnel dielectric layer, which includes alternate insulating portion and conductive portion of substantially equal thickness; creating an implanting window in the insulating portion for performing ion-implantation therethrough to define a source region; removing a part of the conductive portion to form a floating gate structure; providing an insulating material around the floating gate structure; applying a control gate layer over the floating gate structure, which is patterned to form a control gate structure; and defining a drain region on the substrate.
Preferable, the formation of the floating gate layer includes steps of: applying a conductive layer onto the tunnel dielectric layer; creating a trench in the conductive layer; forming an insulating layer on the substrate with the trench and the conductive layer, which fills the trench; and performing a polishing procedure to make the insulating portion and the conductive portion have a substantially equal thickness. Preferably, the insulating structure around the floating gate structure includes a top insulating portion formed by thermal oxidation of a second portion of the conductive portion before the first
Booth Richard
Matthews, Collins, Shepherd & McKay, P.A.
Winbond Electronics Corporation
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