Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-06-09
2001-01-09
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S182000
Reexamination Certificate
active
06171937
ABSTRACT:
BACKGROUND OF THE INVENTION
With regard to fast circuits, there is increasing interest directed towards silicon or silicon-germanium MOSFETs having a short channel length. Switching times in the region of 10 ps can be achieved with silicon short-channel MOS transistors having channel lengths of less than 100 nm. The channel length is in this case given by the dimension of the gate electrode minus gate-source and gate-drain overlap.
IBM TDB Volume 33, June 1990, pages 75 to 77 discloses structuring the gate electrode for a short-channel transistor using a spacer as an etching mask.
Furthermore, it is known (see, for example, U.S. Pat. No. 5 231 038 and German Reference DE 42 34 777 A1) to reduce the structure size, which determines the channel length, of the gate electrode at the surface of the channel by producing the gate electrode with a T-shaped cross-section. For this purpose, insulating spacers are formed on flanks, which face the channel region, of connections of the source/drain regions, above which spacers the gate electrode is formed. The gate electrode laterally overlaps the insulating spacers in the upper region. As an alternative (see German Reference DE 42 34 777 A1), the gate electrode is formed from two different metal layers. Following the structuring of the upper metal layer, the lower metal layer is etched back below the lateral dimensions of the upper metal layer.
At switching speeds of this type, the RC constants of the gate electrodes are no longer negligible. In addition, the resistance of the gate electrode, which is usually composed of polysilicon, which is doped and possibly silicide-treated or coated with other materials of better conductivity, rises with shorter edge length, which is attributed, for example, to grain boundary influences.
SUMMARY OF THE INVENTION
The invention is based on the problem of specifying a method for the production of a MOS transistor having a short channel length.
In general terms the present invention is a method for the production of an MOS transistor. A source region, a drain region and a channel region arranged in between are produced in a substrate, which comprises silicon at least in the region of a main area. A gate dielectric, which covers at least the surface of the channel region, is produced on the main area. A first electrode layer is produced over the whole area. Auxiliary structures having flanks which are aligned essentially perpendicular to the main area are produced on the first electrode layer. Spacers are formed on the flanks of the auxiliary structures. The first electrode layer is structured in accordance with the spacers, electrode webs being produced. A planarizing layer is formed such that the electrode webs are exposed in the upper region, whereas the interspaces between neighboring electrode webs are filled by the planarizing layer. A second electrode layer is produced over the whole area. By structuring the second electrode layer, a gate electrode is formed from a part of one of the electrode webs and a part of the second electrode layer.
Advantageous developments of the present invention are as follows.
An auxiliary layer is applied to the first electrode layer in order to form the auxiliary structures. The auxiliary layer is structured by anisotropic etching such that the first electrode layer remains covered by the auxiliary layer and that depressions having essentially vertical flanks are formed in the auxiliary layer.
The spacers on the flanks of the auxiliary structures are formed by the deposition and anisotropic etching of a layer with essentially conformal edge covering. A hard mask is formed by anisotropic etching of the auxiliary layer, using the spacers as an etching mask. The electrode webs are formed by anisotropic etching of the first electrode layer, using the hard mask as an etching mask.
An insulating layer is deposited in order to form the planarizing layer, the thickness of which insulating layer is at least as large as half the distance between neighboring electrode webs. The insulating layer is removed by a planarization method until the electrode webs are exposed in the upper region. An LDD implantation is carried out following the formation of the electrode webs. The second electrode layer is structured using a lithographically produced mask.
The planarizing layer is formed such that the upper region of the electrode webs distinctly projects beyond the planarizing layer. A mask is produced which covers that part of the electrode webs which are provided as part of the gate electrode. Those parts of the electrode webs which are not covered by the mask are etched back and the mask is removed. Anisotropic etching is carried out following the formation of the second electrode layer, during which anisotropic etching those parts of the electrode webs which are not covered by the mask are removed. Following the formation of the gate electrode, the planarizing layer is structured by anisotropic etching, the gate electrode acting as a mask. An implantation is carried out in order to form the source region and the drain region, the gate electrode acting as a mask. The gate electrode and also the source region and drain region are provided with a layer made of metal silicide. The first electrode layer and the second electrode layer and also the spacers made of doped polysilicon, the auxiliary structures and the planarizing layer are formed from SiO
2
.
The MOS transistor produced according to the invention has a gate electrode having a T-shaped cross-section. The gate electrode has smaller structure sizes in the lower region, at the surface interfacing with the gate dielectric, than in the upper region. The upper region of the gate electrode, which is remote from the gate dielectric, determines the line resistance of the gate electrode. The lower region of the gate electrode at the interface with the gate dielectric, on the other hand, determines the channel length, which is decisive for the switching speed of the MOS transistor. Since the structure sizes of the gate electrode in the MOS transistor according to the invention have different magnitudes at the surface interfacing with the gate dielectric and at the opposite surface, which determines the line resistance of the gate electrode, the channel length is set independently of the contact resistance of the gate electrode.
The MOS transistor produced according to the invention can be used particularly advantageously with channel lengths of less than 100 nm, since in this range the resistance of a polysilicon-containing gate electrode rises more markedly, owing to the increasing influence of grain boundaries, than would correspond to the reduction in the surface area.
A further advantage of the MOS transistor produced according to the invention resides in the fact that even with channel lengths of less than 100 nm, it is possible to realize the gate electrode with structure sizes of ≧250 nm, for example, in the upper region. This enables a further reduction in the resistance of the gate electrode to be achieved by applying metal silicide, for example titanium silicide. It has been shown that, with structure sizes of less than 250 nm, titanium silicide increasingly has a phase of high resistance and is not well suited for resistance reduction with such small structures.
The gate electrode of the MOS transistor is preferably produced from two electrode layers in two independent structuring steps. In this case, a first electrode layer is first of all structured with the aid of a spacer technique in such a way that it determines the channel length of the MOS transistor. As an alternative, the first electrode layer can also be structured by means of a different fine-structuring technique, for example with the aid of electron beam lithography. A planarizing layer is subsequently formed in such a way that the structured, first electrode layer is exposed in the upper region. Outside the structured, first electrode layer, the surface of the gate dielectric is covered by the planarizing layer. A second electrode layer is subsequently depos
Jr. Carl Whitehead
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
Vockrodt Jeff
LandOfFree
Process for producing an MOS transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for producing an MOS transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for producing an MOS transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2435582