Process for producing a silicon capacitor

Details Process for producing a silicon capacitor Process for producing a silicon capacitor

1997-02-10

1999-02-02

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438249, 438392, H01L 218242

Patent

active

058664521

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates generally to a process of producing a capacitor in a hole of a silicon substrate.
2. Description of the Related Art
European Patent Application EP 0 528 281 discloses a silicon capacitor. This comprises an n-doped silicon substrate whose surface is structured in a characteristic way by an electrochemical etching in a fluoride-containing, acidic electrolyte in which the substrate is connected as an anode. In the electrochemical etching, more or less regularly arranged hole structures form at the surface of the substrate. The hole structures have an aspect ratio up into the region of 1:1000. The surface of the hole structures is provided with a dielectric layer and a conductive layer. The conductive layer, dielectric layer and silicon substrate form a capacitor in which, owing to the increase in surface brought about by the hole structures, specific capacitances of up to 100 .mu.FV/mm.sup.3 are achieved. In order to increase the conductivity of the substrate, it is proposed to provide an n.sup.+ -doped zone at the surface of the hole structures.
Normally, silicon capacitors are produced in silicon wafers. In this process, a bending of the silicon wafers is detected which is associated with mechanical strains due to the n.sup.+ -doped zone at the surface of the hole structures, which are up to 300 .mu.m deep. This bending of the silicon wafer results in problems in further process steps such as lithography, reduction in wafer thickness and chip separation, which are necessary for incorporating the silicon capacitor in a package.
The publication by A. Fukuhara et al., J. Appl. Cryst. (1980), vol. 13, pages 31 to 33 discloses a study of the compensation for mechanical strains in silicon crystals. A strain is observed which is essentially proportional to the dopant concentration and which can be compensated for by an additional doping with germanium. Layers 1 to 5 .mu.m deep are doped with germanium and/or boron. The germanium is introduced by diffusion, an annealing time of 14 days being necessary at a temperature of 1473 degrees K.
The publication by A. Heuberger, Mikromechanik, Springer-Verlag 1989, pages 216-236 discloses that highly boron-doped silicon layers which are used as etch-stop layers in micromechanics and which are grown epitaxially on silicon substrates cause bends in substrates which are compensated for by additionally introducing, for example, germanium into the boron-doped layer.


SUMMARY OF THE INVENTION

The present invention provides a further method of producing a silicon capacitor in which a bending of the silicon substrate is avoided and which can be used in a manufacturing process.
According to the present invention, this object is achieved by a method of producing at least one silicon capacitor, wherein a multiplicity of hole apertures is generated by electrochemical etching in a principal surface of an n-doped silicon substrate, wherein a conductive zone provided with electrically active dopant is generated along the surface of the hole apertures, wherein a germanium-doped layer, by means of which the conductive zone is doped with germanium, is generated on the surface of the hole apertures, wherein a dielectric layer and a conductive layer are applied to the surface of the conductive zone, and wherein the conductive layer and the conductive zone are each provided with a contact. Further developments of the invention include the conductive zone being doped with germanium by outdiffusion from the germanium-doped layer. The germanium-doped layer is deposited by CVD deposition at atmospheric pressure using a process gas containing Ge(OCH.sub.3).sub.4 and Si(OC.sub.2 H.sub.5).sub.4.
Preferably, a silicon layer which is doped with germanium in situ by adding a germanium-containing compound during the epitaxy is formed by epitaxy on the surface of the hole apertures. A further undoped silicon layer is grown by epitaxy on the germanium-doped silicon layer, wherein the conductive zone is formed in the german

REFERENCES:
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patent: 4889492 (1989-12-01), Harden et al.
patent: 5354710 (1994-10-01), Kawaguchi et al.
patent: 5500385 (1996-03-01), Wendt et al.
patent: 5759903 (1998-06-01), Lehmann et al.
S. Fisher et al., "Characterizing B-, P-, and GE-Doped Silicon Oxide Films for Interlevel Dielectrics", Sep. 1993, Solid State Technology, pp. 55-64.
A. Fukuhara et al., "X-Ray Bragg Reflexion and Strain Compensation in Silicon Crystals", J. Appln. Cryst., 1980, pp. 31-33.
A. Heuberger, "Mikromechanik", Mikrofertigung mit Methoden der Halbreitertechnolgie, Springer-Verlag Berlin Heidelberg, New York, London, Paris, Tokyo 1989, pp. 216-237.

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