Process for producing a layer arrangement, and layer...

Details Process for producing a layer arrangement, and layer... Process for producing a layer arrangement, and layer...

2007-12-25

2007-12-25

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21623

Reexamination Certificate

active

11178251

ABSTRACT:
The invention relates to a process for producing a layer arrangement, in which, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate, a first semiconductor layer is formed on the sacrificial layer, a first electrically insulating layer is formed on the first semiconductor layer, an electrically conductive layer is formed on the first electrically insulating layer, which electrically conductive layer is laterally patterned, the first electrically insulating layer, the sacrificial layer and the first semiconductor layer are jointly laterally patterned using the laterally patterned electrically conductive layer as a mask, a semiconductor structure is formed adjacent to side walls of the patterned sacrificial layer and of the patterned first semiconductor layer, a substrate is secured over the patterned electrically conductive layer, material of the auxiliary substrate is removed, so that the sacrificial layer is uncovered, the sacrificial layer is selectively removed, so as to form a trench, and a second electrically insulating layer is formed in the trench, then an electrically conductive structure is formed on this second electrically insulating layer.

REFERENCES:
patent: 2006/0022264 (2006-02-01), Mathew et al.
patent: 102 23 719 (2003-11-01), None
patent: 102 23 709 (2003-12-01), None
“Silicon Wafer Bonding Technology for VSLI and MEMS applications”; Iyer, SS, Auberton-Herve, AJ (eds.), Inspec IEE, 2002.
Tserept, A., et al.; “Dry etching of porous silicon in high density plasmas”; phys.stat.sol. (a) 197, No. 1, pp. 163-167 (2003).
Lehmann, Volker; “Electrochemistry of Silicon”, Chapter 6, Wiley-VCH- Verlag, 2002.

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