Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-27
2003-11-11
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S396000, C257S306000
Reexamination Certificate
active
06645809
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a process for producing a capacitor configuration.
In highly integrated memory devices, the information contents of the memory cells are, for example, recorded and provided through the use of appropriate capacitors. During the production of the memory devices or the memory cells on a semiconductor substrate, these capacitors are formed on the semiconductor substrate by using a structuring process and are wired appropriately. In the case of highly integrated circuits, the space required by the individual components, in particular therefore also the space required for the storage capacitors, is a significant factor.
It has therefore been proposed to form a plurality of substantially mutually independent storage capacitors in relation to an electrode in each case, for example the lower or bottom electrode, to be electrically connected to one another, so that the capacitors connected in this way can be formed physically particularly closely adjacent to one another, since specific contacts or lines can be used jointly and do not have to be formed multiple times. In this case, each capacitor is provided with its lower or bottom electrode on a carrier, on which, at least partly, a dielectric layer is provided, which is then followed, at least partly, by the separately provided upper or top electrodes. In order to develop the concept of the capacitor chain, an appropriate electrical connection has to be provided, for example in relation to the lower or bottom electrodes.
In known capacitor configurations having capacitor chains, in particular in the case of chain FeRAMs (Ferroelectric Random Access Memories) or CFRAMs (Chain Ferroelectric Random Access Memories), as they are called, it is a problem that the size of the storage capacitors cannot be below a specific minimum size of the storage capacitors, because of the functional reliability that needs to be provided. This applies even if, instead of a two-dimensional, planar capacitor configuration, three-dimensional capacitor configurations are provided by using corresponding side walls of three-dimensional structures.
In addition, when complying with all the rules on how to configure such a semiconductor component, it is currently not possible to achieve the necessary theoretical cell areas or capacitor areas. This is because the corresponding capacitors have to be formed larger than would be absolutely necessary, because of the production process.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a process for producing a capacitor configuration, and a corresponding capacitor configuration, which overcome the above-mentioned disadvantages of the heretofore-known processes and configurations of this general type and in which the capacitors in the capacitor configuration are formed in a particularly space-saving way on a carrier.
With the foregoing and other objects in view there is provided, in accordance with the invention, a process for producing a capacitor configuration having a plurality of capacitors with a common contact region, the process includes the steps of:
forming a first electrode region on a surface region of a carrier;
forming at least one dielectric region at least partly on the first electrode region;
forming a common, substantially coherent second electrode region by directly applying an electrode material to the at least one dielectric region; and
forming a plurality of second electrodes by structuring the common, substantially coherent second electrode region such that the second electrodes are formed over regions of the first electrode region covered by the at least one dielectric region and such that the second electrodes are not in direct electrical contact with one another.
In other words, in the process for producing a capacitor configuration, in particular a memory device or the like having a plurality of capacitors on a carrier, in particular on a semiconductor substrate or the like, having a common contact region, at least one first electrode region is formed on a surface region of the carrier. Furthermore, at least one dielectric region is formed, at least partly, on the first electrode region. Furthermore, at least one second electrode region is formed, at least partly, on the dielectric region.
The process according to the invention for producing a capacitor configuration is characterized in that, on the first electrode region, on regions thereof covered by the dielectric region, a plurality of second electrode regions which are substantially at least not in direct electrical contact are formed.
It is therefore a basic idea of the process according to the invention to form a plurality of spatially separated and/or independent second electrode regions on a common first electrode region covered by a dielectric. Through the use of this procedure, a corresponding plurality of mutually closely adjacent capacitors is formed, the first common electrode region being used jointly by all the capacitors as one electrode, for example as a bottom electrode. The second electrode regions located opposite the first electrode region which, for example, is formed as a bottom electrode, are at least not in direct electrical contact with one another and thus in each case form the corresponding mating electrode for each capacitor in the plurality of capacitors. The advantage of this procedure, as compared with the prior art, is that it is no longer necessary for a separate first electrode region to be formed on the carrier for each individual capacitor in the capacitor configuration. The separation of the capacitors is therefore provided by the spatial separation of the second electrode regions with respect to their physical distance and with respect to their electrical insulation. This capacitor configuration or capacitor chain therefore substantially uses one electrode jointly, so that an additional connecting device needed in the prior art in the form of a connecting region or the like is not needed. In addition to possible further miniaturization and higher integration of the capacitor configuration, its production is thus also simplified since it is precisely the application or structuring of the additional connecting regions for the connected first electrodes or bottom electrodes that can be dispensed with. As a result, a corresponding lithography step or the like becomes obsolete.
According to a particularly preferred embodiment of a process according to the invention, provision is made for at least part of the plurality of second electrode regions to be formed by direct application of an appropriate electrode material to the respective dielectric region. In the case of this measure, therefore, the configuration of the second electrode regions is brought about directly through the use of the process of applying the appropriate material.
On the other hand, it is advantageous for at least part of the plurality of second electrode regions to be formed by applying a common and substantially coherent second electrode region to the dielectric region and then by subsequently structuring it. As opposed to the aforementioned procedure, therefore, here first of all a specific region of the dielectric region or else the entire dielectric region is substantially coherently coated with the material for the second electrode regions. The structuring of the individual separate second electrode regions is then carried out through the use of subsequent appropriate structuring, for example by using a mask/etching process.
In another embodiment of the process according to the invention, a plurality of dielectric regions that are substantially at least not in direct contact is formed on the first electrode region. This has the advantage that as a result of the provision of a plurality of separate and thus spatially separated dielectric regions, prestructuring on the first electrode region is carried out with regard to the second electrode regions to be formed.
The formation of the plurality of dielectric regions is advantageousl
Hönigschmid Heinz
Röhr Thomas
Cao Phat X.
Doan Theresa T.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
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