Process for preventing misalignment in split-gate flash memory c

Details Process for preventing misalignment in split-gate flash memory c Process for preventing misalignment in split-gate flash memory c

1997-12-11

1999-08-17

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438266, 438401, H01L 218247

Patent

active

059407069

ABSTRACT:
A select transistor for flash memory cells is made by the following steps. Over the blanket second dielectric layer, and an oxynitride layer form a channel mask for patterning the drain and floating gate. Etch the oxynitride layer through the mask to form a channel alignment mask down to a silicon nitride layer with a drain region opening and a floating gate opening. Etch the floating gate opening through the second dielectric layer. Form a polyoxide region in the floating gate layer at the bottom of the floating gate opening by reacting the exposed portion of the floating gate layer with a reactant. Form a drain region in the substrate. Etch away the oxynitride layer and the silicon nitride layer. Pattern the floating gate electrode by etching away the floating gate layer except below the polyoxide region. Form an interelectrode dielectric layer and a second gate electrode layer over the drain region and a portion of the polyoxide region. Form a source region in the substrate self-aligned with the polyoxide region.

REFERENCES:
patent: 5047816 (1991-09-01), Cuevas
patent: 5242848 (1993-09-01), Yeh
patent: 5385856 (1995-01-01), Hong
patent: 5408115 (1995-04-01), Chang
patent: 5702965 (1997-12-01), Kim

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