Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-07-20
2002-06-25
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S555000, C438S301000
Reexamination Certificate
active
06410388
ABSTRACT:
FIELD OF THE INVENTION
This invention relates, generally, to processes for fabricating semiconductor devices and, more particularly, to processes for fabricating non-volatile semiconductor devices, such as electrically-erasable-programmable-read-only memory (EEPROM) devices.
BACKGROUND OF THE INVENTION
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only-memory (PROM), erasable-programmable-read-only-memory (EPROM), and electrically-erasable-programmable-read-only memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. The floating-gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate. The floating-gate electrode together with the source and drain regions forms an enhancement transistor. By storing electrical charge on the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively high value. Correspondingly, when charge is removed from the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively low value. The threshold level of the enhancement transistor determines the current flow through the transistor when the transistor is turned on by the application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state.
Non-volatile memory designers have taken advantage of the ability of silicon nitride to store charge in localized regions and have designed memory circuits that utilize two regions of stored charge within the ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM. The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two-bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
While the recent advances in EEPROM technology have enabled memory designers to double the memory capacity of EEPROM arrays using two-bit data storage, numerous challenges exist in the fabrication of material layers within these devices. In particular, fabricating the p-type and n-type regions within a memory cell presents several challenges. Sometimes, in the fabrication of a memory cell, an ONO layer is formed having a first silicon dioxide layer overlying the semiconductor substrate, a silicon nitride layer overlying the first silicon dioxide layer, and a second silicon dioxide layer overlying the silicon nitride layer. A layer of photoresist is then spun on the ONO layer. The photoresist is patterned into a resist mask and the semiconductor substrate is doped with a p-type dopant, such as boron, using ion implantation at a large angle of incidence relative to the principal surface of the semiconductor substrate to allow the p-type dopant implant to be located away from a subsequent n-type dopant. The wafer is then rotated 180° and the semiconductor substrate is doped a second time with a p-type dopant using ion implantation at a large angle of incidence relative to the principal surface of the semiconductor substrate. Doping the semiconductor substrate with a p-type dopant creates p-type regions. The semiconductor substrate is then doped with an n-type dopant such as arsenic using ion implantation at an angle substantially normal to the principal surface of the semiconductor substrate. Doping the semiconductor substrate with n-type dopants creates n-type regions. Typically, the ONO layer is etched before the semiconductor substrate is doped with n-type dopants in order to make the implant of n-type dopants a more controlled implant. Once the n-type dopants have been implanted in the semiconductor substrate, the resist mask is stripped and cleaned from the ONO layer and a bit-line oxide region is thermally grown onto the semiconductor substrate.
There are several problems that occur with the above-described prior art method for fabricating a memory cell. One problem is that the resist mask has to meet two conflicting requirements: the resist mask has to be thin enough to accommodate the large angle of incidence of the p-type dopant implant, and yet the resist mask has to be thick enough to withstand the n-type dopant implant. If the resist mask is too thick, the p-type dopant implant must be made with a smaller angle of incidence, however if the resist mask is too thin the n-type dopant implant cannot be made at all because the resist mask would have been too heavily degraded. Accordingly, advances in memory cell fabrication technology are necessary to insure patterning of high density memory cells used in two-bit EEPROM devices.
BRIEF SUMMARY
The present invention is for a process for fabricating a memory cell in a two-bit EEPROM device. Fabrication of a two-bit EEPROM device requires the formation of p-type regions and n-type regions with good critical dimension control. This is because proper functionality of the two-bit EEPROM device during a programming operation requires voltages to be applied to the p-type regions and n-type regions. In particular, the p-type regions must be positioned at the edges of the ONO layer for fabrication of high density devices. By fabricating a high quality memory cell using an annealing operation to laterally diffuse the p-type dopant, a high-density two-bit EEPROM device with good critical dimensions control can be manufactured.
In one form, a process for fabricating a memory cell includes providing a semiconductor substrate and forming an ONO layer over the semiconductor substrate. The semiconductor substrate is then preferably doped with a p-type dopant such as boron. Preferably, the p-type dopant implant is a direct implant, which is an implant at an angle substantially normal with respect to the principal surface of the semiconductor substrate. After doping the semiconductor substrate with p-type dopants, the semiconductor substrate is annealed, preferably in a rapid thermal annealing system at a temperature of about 900° C. to about 1050° C. During the annealing process the p-type dopant is laterally diffused so that some of the p-type dopant is below the ONO layer. After the annealing process, the semiconductor substrate is doped with an n-type dopant such as arsenic, preferably by using ion implantation. The doping of the semiconductor substrate with an n-type dopant causes n-type regions to form in the semiconductor substrate. The n-type dopant forces the p-type dopant to the p-type regions under and near the edges of the ONO layer. The annealing step prior to implanting the n-type dopant laterally diffuses the p-type dopant for the formation of pocket regions and removes the need for an angled implant and the problems associated with an angled implant. By avoiding the angled implant, the annealing step allows for the fabrication of a memory cell with tighter critical dimensions.
REFERENCES:
patent: 6121666 (2000-09-01), Burr
patent: 6255174 (2001-07-01), Yu
patent: 1091418 (2001-04-01), None
Foote David K.
Halliyal Arvind
Kluth George Jonathan
Park Stephen K.
Amin & Turocy LLP
Everhart Caridad
LandOfFree
Process for optimizing pocket implant profile by RTA implant... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for optimizing pocket implant profile by RTA implant..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for optimizing pocket implant profile by RTA implant... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2979405