Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-03
2003-05-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S268000, C438S558000
Reexamination Certificate
active
06569738
ABSTRACT:
FIELD OF IN THE INVENTION
This invention relates to power MOSFETs and in particular to a trench-gated power MOSFET with superior on-resistance and breakdown characteristics. This invention also relates to a process for manufacturing such a MOSFET.
BACKGROUND OF THE INVENTION
A conventional trench-gated power MOSFET
10
is shown in the cross-sectional view of FIG.
1
. MOSFET
10
is formed in an N+ semiconductor substrate
11
, on which an N-epitaxial layer
12
is grown. A gate
13
is formed in a trench
14
which extends downward from the top surface of the N-epitaxial (N-epi) layer
12
. The gate is typically made of polycrystalline silicon (polysilicon) and is electrically isolated from the N-epi layer
12
by an oxide layer
15
. The voltage applied to the gate
13
controls the current flowing between an N+ source
16
and a drain
18
, through a channel located adjacent the wall of the trench
14
in a P-body
17
. Drain
18
includes the N-epi layer
12
and N+ substrate
11
. A metal contact layer
19
makes electrical contact with the N+ source
16
and with the P-body
17
through a P+ body contact region
20
. A similar metal contact layer (not shown) typically provides an electrical connection with the bottom side of the drain
18
.
Ideally, the MOSFET would operate as a perfect switch, with infinite resistance when turned off and zero resistance when turned on. In practice, this goal cannot be achieved, but nonetheless two important measures of the efficiency of the MOSFET are its on-resistance and avalanche breakdown voltage (hereinafter “breakdown voltage”). Another important criterion is where the breakdown occurs. Since the drain is normally biased positive with respect to the source, the junction
21
is reverse-biased, and avalanche breakdown normally occurs at the corner of the trench, where the electric field is at a maximum. Breakdown creates hot carriers which can damage or rupture the gate oxide layer
15
. It is therefore desirable to design the device such that breakdown occurs in the bulk silicon, away from the trench
14
.
Another important characteristic of a MOSFET is its threshold voltage, which is the voltage that needs to be applied to the gate in order to create an inversion layer in the channel and thereby turn the device on. In many cases it is desirable to have a low threshold voltage, and this requires that the channel region be lightly doped. Lightly doping the channel, however, increases the risk of punchthrough breakdown, which occurs when the depletion region around the junction
21
expands so as to reach all the way across the channel to the source. The depletion region expands more rapidly when the body region is more lightly doped.
One technique for reducing the strength of the electric field at the corners of the trench and promoting breakdown in the bulk silicon away from the trench is taught in U.S. Pat. No. 5,072,266 to Bulucea et al. (the “Bulucea patent”) This technique is illustrated in
FIG. 2
, which shows a MOSFET
25
, which is similar in MOSFET
10
of
FIG. 1
except that a deep P+ diffusion
27
extends downward from the P-body
17
to a level below the bottom of the trench. Deep P+ diffusion
27
has the effect of shaping the electric field in such a way as to reduce its strength at the corner
29
of the trench.
While the technique of the Bulucea patent improves the breakdown performance of the MOSFET, it sets a lower limit on the cell pitch, shown as “d” in
FIG. 2
, because if the cell pitch is reduced too much, dopant from the deep P+ diffusion will get into the channel region of the MOSFET and increase its threshold voltage. Reducing the cell pitch increases the total perimeter of the cells of the MOSFET, providing a greater gate width for the current, and thereby reduces the on-resistance of the MOSFET. Thus, the net effect of using the technique of the Bulucea patent to improve the breakdown characteristics of the MOSFET is that it becomes more difficult to reduce the on-resistance of the MOSFET.
To summarize, the design of a power MOSFET requires that a compromise be made between the threshold and breakdown voltages and between the on-resistance and breakdown characteristics of the device. There is thus a clear need for a MOSFET structure that avoids or minimizes these compromises without adding undue complexity to the fabrication process.
SUMMARY OF THE INVENTION
In accordance with this invention a power MOSFET is formed in a semiconductor substrate of a first conductivity type which is overlain by an epitaxial layer of a second conductivity type. A trench is formed in the epitaxial layer. The power MOSFET also includes a gate positioned in the trench and electrically isolated from the epitaxial layer by an insulating layer which extends along the side walls and bottom of the trench. The epitaxial layer comprises a source region of the first conductivity type, the source region being located adjacent a top surface of the epitaxial layer and a wall of the trench; a base or body of the second conductivity type; and a drain-drift region of the first conductivity type extending from the substrate to the bottom of the trench, a junction between the drain-drift region and the body extending from the substrate to a side wall of the trench. The power MOSFET can optionally include a threshold adjust implant, and the epitaxial layer can include two or more sublayers having different dopant concentrations (“stepped epi layer”).
In an alternative embodiment the trench extends through the entire epitaxial layer and into the substrate, and there is no need for the drain-drift region.
This invention also includes a process of fabricating a power MOSFET comprising providing a substrate of a first conductivity type; growing an epitaxial layer of a second conductivity type opposite to the first conductivity type on the substrate; forming a trench in the epitaxial layer; introducing dopant of the first conductivity type through a bottom of the trench to form a drain-drift region, the drain-drift region extending between the substrate and the bottom of the trench; forming an insulating layer along the bottom and a sidewall of the trench; introducing a conductive gate material into the trench; and introducing dopant of the first conductivity type into the epitaxial layer to form a source region, the drain-drift region and the source region being formed under conditions such that the source region and drain-drift region are separated by a channel region of the epitaxial layer adjacent the side wall of the trench. Alternatively, the trench can be made to extend through the epitaxial layer to the substrate.
In a variation of the process, a drain dopant is implanted to form a buried layer near the interface between the epitaxial layer and the substrate and then up-diffused until it reaches the bottom of the trench.
Alternatively, a body dopant may be implanted into a lightly doped N−- or P−- epitaxial layer and driven in until it reaches the interface between the epitaxial layer and the substrate, thereby forming a body region.
A MOSFET of this invention has several advantages, including the following. Because the drain-drift region is surrounded laterally by a second conductivity type portion of the epitaxial layer, more effective depletion occurs and more first conductivity type dopant can be put into the drain-drift region, thereby decreasing the on-resistance of the MOSFET. Because the profile of the dopant in the channel region is relatively flat, the MOSFET can be made less vulnerable to punchthrough breakdown without increasing its threshold voltage. Since the second conductivity type portions of the epitaxial layer extend to the substrate except in the areas of the drain-drift region, there is no need to form an additional second conductivity type layer for terminating the device. The separate mask for the deep diffusion of the Bulucea patent and the termination region can be eliminated. Eliminating the deep body diffusion of the Bulucea patent allows for increased cell
Niebling John F.
Roman Angel
Siliconix Inc.
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