Process for manufacturing semiconductor memory device having...

Details Process for manufacturing semiconductor memory device having... Process for manufacturing semiconductor memory device having...

2002-05-24

2003-07-08

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S261000, C438S264000, C438S266000, C438S424000

Reexamination Certificate

active

06589844

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. HEI 11 (1999)-218971, filed on Aug. 2, 1999, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor memory device. More particularly, it relates to a process for manufacturing a semiconductor memory device having floating gates and control gates in which insulating films are provided between the floating gates.
2. Description of Related Art
In the field of semiconductor memory devices having floating gates and control gates, a technique for increasing a coupling ratio [C
2
/(C
1
+C
2
), C
1
: a coupling capacitance between a floating gate and a semiconductor substrate, C
2
: a coupling capacitance between a floating gate and a control gate] has been proposed with the intension of reducing voltage, for example, by Japanese Unexamined Patent Publication No. HEI 9-102554.
Hereinafter, a process for manufacturing a semiconductor memory device based on this technique will be explained. FIGS.
14
(
a
) to
14
(
g
) are sectional views taken along the line X-X′ in FIG.
13
(
a
) and FIGS.
14
(
a
′) to
14
(
g
′) are sectional views taken along the line Y-Y′ in FIG.
13
(
a
).
First, as shown in FIGS.
14
(
a
) and
14
(
a
′), a tunnel oxide film
22
of about 10 nm thick is formed on an active region of a p-type semiconductor substrate
21
by thermal oxidization. Then, a phosphorus-doped polysilicon film
23
of 100 to 200 nm thick is formed thereon as a material for a lower floating gate. A resist film is formed thereon and patterned by photolithography to form a resist pattern R
1
(see FIG.
13
(
b
)). Using the resist pattern R
1
as a mask, the polysilicon film
23
and the tunnel oxide film
22
are sequentially etched into a floating gate by reactive ion etching (RIE) method.
Next, as shown in FIGS.
14
(
b
) and
14
(
b
′), using the resist pattern R
1
and the polysilicon film
23
as a mask, arsenic ions, for example, are implanted at an angle inclined by 7° from a normal line with respect to the substrate surface (hereinafter abbreviated as “at 7°”) at an implantation energy of 70 keV in a dose of 1×10
15
/cm
2
to form a high concentration impurity layer
29
.
As shown in FIGS.
14
(
c
) and
14
(
c
′), the resist pattern R
1
is removed and then phosphorus ions, for example, are implanted along the direction perpendicular to the substrate surface (hereinafter abbreviated as “at 0°”) at an implantation energy of 50 keV in a dose of 3×10
13
/cm
2
using the polysilicon film
23
as a mask to form a low concentration impurity layer
28
.
Then, as shown in FIGS.
14
(
d
) and
14
(
d
′), the resulting semiconductor substrate
21
is heated at 900° C. for 10 minutes under nitrogen atmosphere to form impurity layers
28
a
and
29
a
in which impurities are activated.
As shown in
FIGS. 14
(
e
) and
14
(
e
′), a silicon oxide film of about 200 to 300 nm thick is formed on the entire surface of the semiconductor substrate
21
by chemical vapor deposition (CVD) method and etched back by RIE method until the polysilicon film
23
is exposed to form a buried insulating film
30
in a space between the floating gates. At this time, the buried insulating film
30
is arranged so that sidewalls of the polysilicon film
23
are partially exposed.
Then, as shown in
FIGS. 14
(
f
) and
14
(
f
′), for increasing the gate coupling ratio, a phosphorus-doped polysilicon film of about 100 nm thick is formed on the entire surface of the semiconductor substrate
21
and etched back by RIE method to form a polysilicon film
31
which will be a projection of the floating gate.
Next, as shown in FIGS.
14
(
g
) and
14
(
g
′), a silicon oxide film of 6 nm thick by thermal oxidation, a silicon nitride film of 8 nm thick by CVD method and a silicon oxide film of 6 nm thick by CVD method are deposited in this order on the semiconductor substrate
21
to form an ONO film
32
as a dielectric film between the floating gate and the control gate. Further, a phosphorus-doped polysilicon film of 100 nm thick and a tungsten silicide film of 100 nm thick are sequentially formed thereon to provide a polycide film of 200 nm thick. A resist film is formed thereon (not illustrated) and patterned into a resist pattern R
3
by photolithography (see FIG.
13
(
b
)). Using the resist pattern R
3
as a mask, the polycide film, the ONO film
32
, the polysilicon film
31
and the polysilicon film
23
are etched successively by RIB method to form a control gate
33
and floating gates
23
a
and
31
a.
The resist pattern R
3
is removed and then boron ions, for example, are implanted at 0°, 10 to 40 keV and 5×10
12
to 5×10
13
/cm
2
using the control gate
33
as a mask to form an impurity layer
34
for memory device isolation.
Thereafter, interlayer insulating film, contact hole and metal wiring are formed by a known technique to complete a semiconductor memory device.
FIG. 15
shows an equivalent circuit diagram of a semiconductor memory device having asymmetric source/drain regions in which a coupling ratio C
2
/C
1
is increased as described above.
In
FIG. 15
, Tr.
00
to Tr.
32
indicate memory cells each having a floating gate, WL
0
to
3
indicate word lines connected to the control gates of the memory cells and BL
0
to
3
are bit lines connected to the common source/drain diffused wiring layers of the memory cells. The word line WL
0
is connected to the control gates of Tr.
00
, Tr.
01
and Tr.
02
, and the word line WL
1
is connected to the control gates of Tr.
10
, Tr.
11
and Tr.
12
, respectively. The bit line BL
1
is connected to the drains of Tr.
01
, Tr.
11
, Tr.
21
and Tr.
31
or the sources of Tr.
00
, Tr.
10
, Tr.
20
and Tr.
30
. The bit line BL
2
is connected to the drains of Tr.
02
, Tr.
12
, Tr.
22
and Tr.
32
or the sources of Tr.
01
, Tr.
11
, Tr.
21
and Tr.
31
.
Table 1 shows operating voltages at reading, writing and erasing in Tr.
11
of FIG.
15
. Further,
FIG. 16
shows a state where information is read from the selected memory cell Tr.
11
,
FIG. 17
a state where information is written in Tr.
11
and
FIG. 18
a state where information is erased from Tr.
10
to Tr.
12
connected to the word line WL
1
including Tr.
11
.
TABLE 1
WL
WL not
BL
BL not
Selected
selected
Selected
selected
SL
Substrate
WL 1
WL 0, 2
BL 1
BL 0, 3
BL 2
PW
Reading
3
0
0
open
1
0
Writing
−12
open
4
open
open
0
Erasing
12
open
−8
−8
−8
−8
Writing in the memory cell is defined as Vth<2V and erasing is defined as Vth>4V.
As shown in FIG.
16
and Table 1, information of the memory cell is read by applying a voltage of 3V to the control gate, grounding the substrate and the drain, and applying a voltage of 1V to the source so as to pass current i.
As shown in FIG.
17
and Table 1, information is written in Tr.
11
by applying −12V to the control gate, grounding the substrate and applying 4V to the drain so that electrons are drawn from the floating gate utilizing a FN tunneling current flowing through a thin oxide film in a region where the drain and the floating gate are overlapped. At this time, a voltage of 4V applied to the drain is also applied to the source of Tr.
10
sharing the common diffused wiring layer with the drain of Tr.
11
. However, a depletion layer is formed within the substrate because the impurity concentration in the source is low and an electric field actually applied to the thin oxide film in the overlapped region of the source and the floating gate is not sufficient to generate the FN tunneling current. As a result, information is selectively written only in the memory cell including the floating gate overlapped with the drain (high concentration impurity layer).
As shown in FIG.
18
and Table 1, information is erased from Tr.
11
by

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