Process for manufacturing semiconductor integrated memory...

Details Process for manufacturing semiconductor integrated memory... Process for manufacturing semiconductor integrated memory...

2000-02-18

2002-04-02

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S266000, C257S316000, C365S185010, C365S185160

Reexamination Certificate

active

06365456

ABSTRACT:

TECHNICAL FIELD
This invention relates to an improved process of manufacturing semiconductor integrated electronic memory devices with cells matrix having virtual ground, and more specifically, to a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel strips.
BACKGROUND OF THE INVENTION
The invention relates, particularly but not exclusively, to a process for manufacturing semiconductor integrated electronic memory devices with cells matrix having virtual ground, and throughout the following description, reference will be made to that technical field for convenience of illustration.
Electronic semiconductor-integrated EPROM or Flash EPROM memory devices include a number of non-volatile memory cells organized in matrix form; that is, the cells arc arranged into rows, or word lines, and columns, or bit lines.
Each non-volatile memory cell has a MOS transistor with a floating gate electrode located above the channel region. This floating gate has a high D.C. impedance to all the other terminals of the same cell and to the circuit in which the cell is incorporated. The cell also has a second electrode, the control gate, which is driven by appropriate control voltages. The other transistor electrodes are, as usual, the drain and source terminals.
In recent years, considerable effort went to the development of memory devices with increased circuit density. This effort resulted in electrically programmable non-volatile memory matrices of the contactless type being developed which have a so-called “tablecloth” or cross-point structure.
An example of matrices of this kind, and their manufacturing process, is described in European Patent No. 0 573 728 to this Applicant, hereby incorporated by reference.
In matrices of this type, the matrix bit lines are formed in the substrate as continuous parallel diffusion strips. These matrices include memory cells which have floating gate capacitive coupling MOS devices.
Conventionally, the process flow for manufacturing these matrices includes forming, on the semiconductor substrate, a stacked ply structure which includes a first layer of gate oxide, first layer of polysilicon, second layer of interpoly oxide, and second layer of polysilicon. An implantation step is then carried out to provide the bit lines, and after the deposition of a planarizing layer, the matrix word lines are formed.
In the prior art, the gate regions of the individual cells are then defined by self-aligned etching. This solution has several drawbacks in that the self-aligned etch step becomes more critical in smaller sized cells.
SUMMARY OF THE INVENTION
Embodiments of the invention provide a process for defining memory cells, arranged into matrices of the crosspoint type, which have structural and functional features that avoids the need for a critical gate region defining step, thereby overcoming the limitations and drawbacks which still beset the memory cells of prior art crosspoint matrices.
In embodiments of the invention, each gate region of the matrix cells is fully defined by an oxide island, before the matrix bit lines are defined.
Presented is a process for manufacturing electronic semiconductor integrated memory devices that begins with growing an oxide layer over a cell matrix region of the memory device. Then, a stack structure is formed that includes a first conductor layer, a first dielectric layer, and a second conductor layer. After that, a second dielectric layer is deposited over the semiconductor. Floating gate regions are defined by photolithography using a mask of “POLY
1
long a first direction”, to define, in the second dielectric layer, a number of parallel strips which delimit a first dimension of floating gate regions. The parallel strips are then etched from the second dielectric layer. Next, a Poly
1
mask is used in a second direction to define a number of dielectric islands in the parallel strips, and the islands are etched. The stack structure and the thin gate oxide layer are then etched to define gate regions of the matrix cells using the oxide island.
The features and advantages of a device according to the invention will become apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.


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patent: 5327378 (1994-07-01), Kazerounian
patent: 5916821 (1999-06-01), Kerber
patent: 5946576 (1999-08-01), Wen
patent: 6001689 (1999-12-01), Van Buskirk et al.
patent: 6080624 (2000-06-01), Kamiya et al.
patent: 195 26 011 (1996-11-01), None
patent: 0 731 501 (1996-09-01), None
patent: 05190809 (1993-07-01), None
Johnson et al., “Method for Making Submicron Dimensions in Structures Using Sidewall Image Transfer Techniques,”IBM Technical Disclosure Bulletin 26(9):4587-4589, Feb. 1984.

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