Process for manufacturing semiconductor integrated circuit devic

Details Process for manufacturing semiconductor integrated circuit devic Process for manufacturing semiconductor integrated circuit devic

1998-04-28

2000-02-29

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438239, H01L 218244

Patent

active

060308656

ABSTRACT:
In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

REFERENCES:
patent: 5162259 (1992-11-01), Kolar et al.
patent: 5483083 (1996-01-01), Meguro et al.
patent: 5631863 (1997-05-01), Fechner et al.
patent: 5635731 (1997-06-01), Ashida
patent: 5652457 (1997-07-01), Ikeda et al.
patent: 5858845 (1999-01-01), Cheffings

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