Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-28
2002-05-14
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S247000, C438S252000, C438S224000
Reexamination Certificate
active
06387744
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a technique for manufacturing a semiconductor integrated circuit device and, more particularly, to a technique which is effective when applied to a well separation technique, by which in order to electrically separate a well (semiconductor region) formed in a semiconductor substrate and the semiconductor substrate, another well is so formed in the bottom and side portions of the former well as to encompass the same.
BACKGROUND OF THE INVENTION
This well separation technique enables a first well formed in a semiconductor substrate to be supplied with a desired voltage different from that applied to the semiconductor substrate, by electrically separating the first well from a second well formed therearound.
This technique is applied to a variety of semiconductor integrated circuit devices such as a DRAM (Dynamic Random Access Memory) in which a memory cell is formed in a first well, for example, to apply a back bias voltage to the MIS•FET (Metal Insulator Semiconductor Field Effect Transistor) of the memory cell, or a flash memory (EEPROM: Electrically Erasable Programmable ROM), in which a negative voltage is applied to the first well.
Here will be described a semiconductor integrated circuit device having a well separation structure examined by us.
At the well separation region in the semiconductor substrate of a second conductivity type, more specifically, there are formed a deep well of a first conductivity type and a shallow well of the second conductivity type which is formed in the region of the deep well. This deep well is formed by diffusing an impurity from the major surface to a deep position of the semiconductor substrate to encompass the outer periphery of the shallow well and to separate the shallow well and semiconductor substrate electrically. As a result, the shallow well can be fed with a voltage different from that to be applied to the semiconductor substrate.
In another region of the semiconductor substrate, there are formed an ordinary well of the first conductivity type and an ordinary well of the second conductivity type. These wells of the first conductivity type and the second conductivity type are formed by diffusing an impurity from the major surface to a predetermined position of the semiconductor substrate.
SUMMARY OF THE INVENTION
In the technique for forming the aforementioned well structure with two masks, the aforementioned well structure is realized with two masks: a common mask for an impurity introducing step to form the deep well of the first conductivity type and the ordinary well of the first conductivity type, and a common mask for an impurity introducing step to form the shallow well of the second conductivity type and the ordinary well of the second conductivity type.
In the technique thus far described for forming the two wells with one mask, however, the following problems have been found out by us.
Specifically, the first problem comes from the fact that the shallow well of the second conductivity type is formed by compensating the impurity of the second conductivity type and the impurity of the first conductivity type. That is, the effective impurity concentration of the second conductivity type increases to about two times as high as that of the second conductivity type in the ordinary well of the second conductivity type having no well separation, so that the transistor to be formed over the major surface of the semiconductor substrate has greatly different characteristics, especially the threshold voltage. A new mask is required to adjust the threshold voltage.
The second problem is that the total impurity concentration of the shallow well of the second conductivity type increases to about three times the impurity concentration of the ordinary well of the second conductivity type which is subjected to no well separation. As a result, the mobility of the carriers in the major surface region of the semiconductor substrate lowers to deteriorate the characteristics of the transistor to be formed over the major surface, especially to reduce the drain current.
The aforementioned two problems become serious as the factors obstructing the higher performance of the transistor as the well density has a tendency to rise more with the further miniaturization of the transistor.
An object of the invention is to provide a technique capable of optimizing the impurity concentrations of a well and an ordinary well in a well separation region without inviting any increase in the number of steps for manufacturing the semiconductor integrated circuit device.
Another object of the invention is to provide a technique capable of improving the characteristics of the elements to be formed in the well and the ordinary well in the well separation region without inviting any increase in the number of steps for manufacturing the semiconductor integrated circuit device.
The aforementioned and other objects and novel features of the invention will become apparent from the following description to be made with reference to the accompanying drawings.
Representatives of the aspects of the invention to be disclosed herein will be briefly summarized in the following.
According to the invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming, by patterning, over a major surface of a semiconductor substrate a first mask through which a first well forming region and a second well forming region formed at a distance from the first well forming region are exposed;
(b) doping the semiconductor substrate with an impurity by using the first mask as an impurity introduction mask so as to form a buried well region of a first conductivity type at a deep position of the semiconductor substrate in the first well forming region;
(c) doping the semiconductor substrate with an impurity by using the first mask as an impurity introduction mask so as to form a shallow well region of a second conductivity type over the buried well region of the first conductivity type in the first well forming region and the well forming region;
(d) forming, by patterning, over the major surface of the semiconductor substrate a second mask through which a third well forming region encompassing the buried well region of the first conductivity type of the first well forming region, and the shallow well region of the second conductivity type and a fourth well forming region formed at a distance from the first well forming region; and
(e) doping the semiconductor substrate with an impurity by using the second mask as an impurity introduction mask so as to form a shallow well region of the first conductivity type encompassing the outer periphery of the shallow well region of the second conductivity type of the first well forming region and electrically connected with the buried well region of the first conductivity type of the first well forming region in the third well forming region and to form a shallow well region of the first conductivity type in the fourth well forming region,
wherein in the first well forming region, the shallow well region of the second conductivity type in the first well forming region is encompassed by the shallow well region of the first conductivity type formed in the third well forming region and the buried well region of the first conductivity type in the first well forming region and is electrically separated from the semiconductor substrate,
wherein in the second well forming region, the shallow well region of the second conductivity type is electrically connected with the semiconductor substrate.
In the invention, moreover, the impurity introduction of the step (e) is so performed that the impurity concentration of at least a portion of the shallow well region of the first conductivity type in the third well forming region is higher than that of the shallow well region of the second conductivity type in the first well forming region.
Moreover, the invention further comprises the steps of:
forming, by patterning, over a major surface of
Hashimoto Takashi
Ikeda Shuji
Kuroda Kenichi
Shukuri Shoji
Taniguchi Yasuhiro
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