Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-31
2001-05-08
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S220000, C438S224000, C438S414000
Reexamination Certificate
active
06228704
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a process for manufacturing semiconductor integrated circuit device and in particular to a process for manufacturing a semiconductor integrated circuit device having a triple-well structure and two types of gate oxide film having different thicknesses in one chip.
BACKGROUND
In a process for manufacturing a semiconductor integrated circuit device having a triple-well structure and two types of gate oxide film having different thicknesses in one chip, a manufacturing process in which ion implantation toward an embedded diffused layer for forming a triple-well and etching of oxide film to form two types of gate oxide film having different thicknesses in one chip is achieved by passing, preferably, one photo resist step has become one of great concerns.
The reason why a configuration having a triple-well structure and two types of gate oxide films having different thicknesses in one chip has been demanded will be described.
Firstly, necessity of a triple-well will be described. Semiconductor integrated circuit devices such as DRAMs (dynamic random access memories) and SRAMs (static random memories) are generally formed with peripheral circuit and input/output units comprising CMOSs. Their silicon substrates are formed with N-type and P-type wells. If the internal power source voltage is made lower than the external power source voltage for reduction in power consumption, it is necessary to insulate N-type wells from each other to which internal and external power source voltages are applied, respectively. In DRAMs and SRAMs, the P-type wells of memory cell unit should be electrically insulated from the other P-type wells for protecting the memory cells from electrical noises from the peripheral and input/output (I/O) circuit units.
In order to electrically insulate N-type wells from each other and P-type wells from each other in such a manner, it is necessary to provide a triple-well structure by forming an embedded diffused layer.
Necessity to use two types of gate oxide film having different thicknesses in one chip will now be described.
If the external and internal power source voltages are different in a semi conductor integrated circuit device such as DRAM and SRAM, a voltage which is higher than that of the peripheral circuit unit to which the internal power source voltage is applied is applied to the gates of MOS transistors of I/O circuit unit, to which external power source voltage is applied.
If the voltage for word line is stepped up in a memory cell unit of DRAMs and SRAMs, a voltage which is higher than that of the peripheral circuit is applied to the gates of MOS transistors of the memory cells.
If only one gate oxide film is used in one chip, the thickness of the gate oxide film should be set to meet the requirements of a MOS transistor to which the highest gate voltage is applied for assuring the reliability of the gate oxide film. Accordingly, if the external and internal power source voltages are different, or stepping up of word line voltage is conducted, the thickness of the gate oxide film should be set to meet the requirements made by the higher voltage of the I/O circuit units and memory cells.
As a result, the gate oxide film having a thickness which is larger than that the film needs will be provided in the peripheral circuit units. The thicker the gate oxide film becomes, the less the turn-on current (the current which flows through the transistor when it is conductive) of the MOS transistor becomes. This results in a low operation speed of the circuit.
On the other hand, if two types of gate oxide films having different thicknesses are formed in one chip, the operation speed of the circuit can be made faster by making the gate oxide film of the peripheral circuit unit thinner than that of the other units to increase the turn-on current of the transistor. In such a manner, it is necessary to use two types of gate oxide films having different thicknesses in one chip for making the operation speed faster.
As mentioned above, the configuration including a triple-well structure and two types of gate oxide films having different thickness in one chip is very useful.
SUMMARY OF THE DISCLOSURE
Japanese patent application No. 10-053912(filed by the same applicant with this application and has not been published yet on filing of this application) which was filed prior to this application discloses a process for implementing the two structures while suppressing an increase in the number of steps.
This process enables the ion implantation of the embedded diffused layer for triple-well formation and etching of an oxide film for forming two types of gate oxide film having different thicknesses in one chip to be carried out through only one PR (photo resist) step.
However, this process has a problem as follows:
An N-type silicon substrate is used. The N-type silicon substrate is more expensive than P-type silicon substrate, resulting in high cost of device manufacturing.
Also even if a cheaper P-type silicon substrate is used, the thickness of the gate oxide film of the I/O circuit units is equal to that of the peripheral circuit units.
Accordingly, if the external voltage source voltage is higher than the inner power source voltage, the thickness of the I/O and peripheral circuit units must be preset to meet the requirements due to the higher external power source voltage.
Accordingly, the gate oxide film of the peripheral circuit units becomes thicker than required in view of reliability to decrease the turn-on current. This results in a slow circuit operation speed. This circuit configuration is not satisfactory in speeding up of the circuit operation.
Therefore, the present invention was made in view of the above mentioned technical problems. It is an object of the present invention to provide a process for manufacturing a semiconductor integrated circuit device in which ion implantation of an embedded diffused layer for forming a triple-well and etching of an oxide film for forming two types of gate oxide film having different thicknesses in one chip by only one PR step, which decreases the cost and speeds up the circuit by making the gate oxide film of the peripheral circuit unit thinner than that of the I/O circuit unit.
Further objects of the present invention will become apparent in the entire disclosure.
According to an aspect of the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device is characterized in that a resist mask having a given width within a given range is formed at a gate forming area where a large thickness is desired of a gate oxide film of an active element in a region where a second conductive type embedded layer is formed in a first conductive type substrate, and in that the given width of the resist mask is preset so that the embedded layer is also formed immediately below said resist mask having the given width when the embedded layer is formed by implanting ions via the resist mask at a given implanting energy.
In another aspect of the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device characterized in that the resist mask is patterned on an oxide film formed on the entire surface of said substrate, and in that the oxide film not covered with the resist mask is removed by using the resist mask as an etching mask followed by forming an oxide film over the entire surface, whereby two types of gate oxide film having different thicknesses are formed in one chip by only one exposure step. The substrate is preferably made of P-type silicon for reduction in cost.
REFERENCES:
patent: 5891780 (1999-04-01), Hasegawa et al.
patent: 251449 (1999-09-01), None
T. Yokoyama et al, Symp. on ULSi Tech. Dig., p. 145.
Bowers Charles
Foley & Lardner
Huynh Yennhu B.
NEC Corporation
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