Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-04-16
2004-08-31
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S265000
Reexamination Certificate
active
06784058
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a process for the same. The invention particularly relates to a nonvolatile memory cell, or the like, as the semiconductor device.
2. Description of the Background Art
Referring to
FIGS. 6
to
8
, a process for a semiconductor device according to a prior art is described. As shown in
FIG. 6
, floating gate electrodes
4
are formed on the main surface of a silicon substrate
1
as a semiconductor substrate with tunnel oxide films
2
intervened. Control gate electrodes
5
are formed above floating gate electrodes
4
with ONO interlayer films
3
intervened. In the case of the example shown in
FIG. 6
, portions of top surfaces of control gate electrodes
5
are covered with TEOS (tetra-ethyl-ortho-silicate) films
8
. A source layer
7
and drain layers
6
are formed in the portions adjoining floating gate electrode
4
, and the like, within the regions (hereinafter referred to as “active regions”) wherein the main surface of silicon substrate
1
is exposed by injecting an impurity from above. In the example shown in
FIG. 6
, the electrodes and drain layer
6
are symmetrically arranged in a form wherein the right and the left memory cells share one source layer
7
in the center of the symmetrical structure in order to reduce the space.
In the case that an impurity, such as arsenic, is injected into the active regions, silicon substrate
1
is locally converted to an amorphous condition due to the effects of the injection. Next, as shown in
FIG. 7
, the entirety of the top surface of this substrate is covered with a TEOS film
9
by means of a CVD (chemical vapor deposition) method, or the like. After this, as shown in
FIG. 8
, the sidewalls of floating gate electrodes
4
are thermally oxidized by carrying out a heat treatment and oxide films
10
are formed so as to cover the sidewalls of floating gate electrodes
4
. Here, the reason why oxide films
10
are formed is in order to prevent electrons, from the sidewalls of floating gate electrodes
4
, from becoming volatile and in order to repair the etching damage. However, in the portions wherein source layer
7
or silicon substrate
1
in the vicinity thereof are converted to an amorphous condition, recrystallization of silicon occurs due to the heat in the heat treatment for forming oxide films
10
. This recrystallization causes crystal defects
11
within silicon substrate
1
. There is a risk that such crystal defects
11
may cause a current leak between source layer
7
and drain layer
6
so as to prevent a normal operation of the semiconductor device. In addition, merely the presence of crystal defects
11
, which may cause the above described malfunction, reduces the reliability of the semiconductor device.
On the other hand, it is known that crystal defects do not easily occur at the time of recrystallization in the case that nitrogen is included in the silicon substrate. Therefore, in order to prevent the occurrence of crystal defects, a method of carrying out lamp annealing in a nitrogen flow can be considered at the stage of FIG.
6
. This lamp annealing is also referred to as “RTP (rapid thermal process) treatment.” In the case that lamp annealing is carried out in a nitrogen flow as shown in
FIG. 9
, though the inclusion of nitrogen in silicon substrate
1
, which is the purpose, can be achieved, at the same time, nitride films
13
are formed on the sidewalls of the exposed floating gate electrodes
4
. In the case that nitride films
13
are once formed in such a manner, the formation of oxide films
10
on the sidewalls of floating gate electrodes
4
cannot be achieved due to blockage by nitride films
13
even when a heat treatment is carried out in a later step, after coverage with TEOS film
9
, as shown in FIG.
10
. When oxide films
10
are not formed, there is a risk that electrons from the sidewalls of floating gate electrodes
4
may become volatized.
Therefore, purposes of the present invention are to provide a semiconductor device of a high reliability wherein electrons from the sidewalls of the floating gate electrodes are prevented from becoming volatized, while crystal defects are prevented from occurring in the semiconductor substrate so that no current leakage is caused as well as to provide a process for the same.
SUMMARY OF THE INVENTION
In order to achieve the above described purposes, a semiconductor device according to the present invention comprises a semiconductor substrate, a floating gate electrode formed above the semiconductor substrate with an oxide film intervened and active regions wherein the surface of the semiconductor substrate is exposed in the positions adjoining both sides of the floating gate electrode, as seen from above, wherein the semiconductor substrate includes impurity injection regions into which an impurity is injected towards the inside of the semiconductor substrate from the active regions, wherein the impurity injection regions include nitrogen over the entirety of the regions and wherein the floating gate electrode includes sidewalls and oxide films formed so as to cover the sidewalls in order to prevent electrons via the sidewalls from becoming volatized. By adopting this structure, a semiconductor device can be gained wherein the occurrence of crystal defects can be prevented at the time of a heat treatment while electrons from the floating gate electrode can be prevented from becoming volatized.
In the above described invention, the above impurity is preferably arsenic. By adopting this structure, arsenic can be easily made to enter the silicon substrate through injection because of its large atomic mass.
In order to achieve the above described purposes, a process for a semiconductor device according to the present invention includes the following steps applied to a semiconductor substrate wherein a floating gate electrode have sidewalls is formed above the semiconductor substrate with an oxide film intervened and wherein the substrate has active regions wherein the surface of the semiconductor substrate is exposed in the positions adjoining both sides of the floating gate electrode, as seen from above, and an impurity is injected into the active regions: the lamp annealing step of carrying out a heat treatment in the atmosphere of a first gas mixture which includes nitrogen and oxygen and the oxide film formation step of carrying out a heat treatment in the atmosphere of a second gas mixture which includes oxygen so as to form an oxide film on the sidewalls after the lamp annealing step. By adopting this process, the active regions can be made to include nitrogen without the formation of a nitride film on the sidewalls of the floating gate electrode in the lamp annealing step. Since a nitride film is not formed on the sidewalls of the floating gate electrode, an oxide film can be formed in a normal manner on the sidewalls of the floating gate electrode in the oxide film formation step.
In the above described invention, a gas mixture which includes no less than 10% and no more than 70% of a volume ratio of oxygen is used as the above first gas mixture. By adopting this process, a nitride film is not formed on the sidewalls of the floating gate electrode and, in addition, the active regions are made to include a sufficient amount of nitrogen.
In the above described invention, the above impurity is preferably arsenic. By adopting this process, arsenic is easily made to enter the silicon substrate through injection because of its large atomic mass.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5371027 (1994-12-01), Walker et al.
patent: 6582998 (2003-06-01), Nitta
patent: 58-121682 (1983-07-01), None
McDermott Will & Emery LLP
Pert Evan
Renesas Technology Corp.
LandOfFree
Process for manufacturing semiconductor device including... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for manufacturing semiconductor device including..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for manufacturing semiconductor device including... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3356971