Process for manufacturing semiconductor device

Details Process for manufacturing semiconductor device Process for manufacturing semiconductor device

2000-12-18

2003-04-08

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S424000, C438S594000

Reexamination Certificate

active

06544843

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese Patent Application No. HEI 11(1999)-359314 filed on Dec. 17, 1999, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor device, more particularly, a process for manufacturing a semiconductor device in which a plurality of protrusions with different widths are formed on a semiconductor substrate so that a recess between adjacent protrusions has a predetermined width and thereafter an element isolation layer is formed in the recess. The present invention is suitably applicable in particular to the manufacture of a semiconductor memory having floating gates and control gates in which source/drain regions are asymmetrically formed in self-alignment with respect to the floating gates and insulating films are placed on the source/drain regions.
2. Description of Related Art
For embedding a chemical vapor deposited (CVD) insulating film in a recess formed by patterning on a semiconductor substrate, generally, the CVD insulating film is deposited in the recess and on a polish stopper film disposed on protrusions, and then flattened by a chemical mechanical polishing (CMP) process. The CVD film is deposited on the stopper film thicker than a thickness required for element isolation, and then the CVD film needs to be polished away to the required thickness.
However, the CMP process has some problem in that, if a polish amount increases, a wide element isolation region is polished and consequently the thickness of the CVD film in the region is decreased (a dishing phenomenon). Therefore, it is difficult to ensure the thickness of the insulating film embedded in the recess.
To cope with this problem, Japanese Unexamined Patent Publication No. HEI 8(1996)-78389 proposes a technique in which the polish amount in the CMP process is decreased. This technique is described as prior art with reference to FIGS.
17
(
a
) to
17
(
c
),
18
(
d
) to
18
(
f
) and
19
(
g
) to
19
(
i
), which illustrate a process for manufacturing a semiconductor device according to an embodiment of the prior art.
A thermal oxide film
2
made of a silicon oxide film is formed in a thickness of about 10 nm in an active region of a P-type semiconductor substrate
1
by thermal oxidation, and a silicon nitride film
5
is formed in a thickness of 200 nm by chemical vapor deposition (CVD). Subsequently, as shown in FIG.
17
(
a
), the silicon nitride film
5
and the thermal oxide film
2
are sequentially etched by reactive ion etching using a resist mask formed by photolithography. Further, the semiconductor substrate
1
is etched to form trenches
161
and 163 of 300 nm depth in the semiconductor substrate
1
(see FIG.
17
(
b
)). Subsequently, a silicon oxide film
17
is formed in a thickness of 20 nm within the trenches by thermal oxidation (see FIG.
17
(
c
)). Thereafter, in a state in which the silicon nitride film
5
to be a stopper layer in a later step remains on protrusions, silicon oxide films
101
to
104
as insulating films are deposited to a thickness of about 350 nm by a high-density plasma enhanced chemical vapor deposition (HDP-CVD) method (see FIG.
7
(
d
)). Thus, triangular silicon oxide films
104
and trapezoid silicon oxide films
102
are formed on the silicon nitride film
5
. The silicon oxide films
102
and
104
on the protrusions are separated from the silicon oxide films
101
and
103
in the recesses by the silicon nitride films
5
which will be stopper layers. Subsequently, as shown in FIG.
18
(
e
), a silicon nitride film
15
which is to be an etching mask layer later is deposited to a thickness of 20 nm on the entire surface by CVD. Then the top of the mask layer
15
on the silicon oxide films
102
and
104
in the protrusions are removed by polishing (see FIG.
18
(
f
)). Subsequently, the etching of the silicon oxide films
102
a
and
104
a
progresses from removed parts of the mask layer
15
by a wet etch-back process (using diluted hydrofluoric acid), to fully expose the top faces of the silicon nitride films
51
and
52
as the stopper layers (see FIG.
19
(
g
)). At this time, the silicon oxide films
101
and
103
in the trenches, which are covered with the mask layers
15
a
and
15
b
, are not etched in this wet etch back process. Thereafter, the silicon nitride films
15
a
and
15
b
as the mask layers and the silicon nitride films
51
and
52
as the stopper layers are removed with heated phosphoric acid (see FIG.
19
(
h
)), and flattening is carried out (see FIG.
19
(
i
)).
Thereafter, though not shown, in order to improve a gate coupling ratio, a poly-crystalline silicon film doped with phosphorus as an impurity is deposited, and then etched by reactive ion etching using a resist film patterned by photolithography as a mask, so as to form upper-layer floating gates. Here, the mask has openings above thick parts of the silicon oxide film so that the silicon oxide film can endure the etch amount of an ONO film when the control film is formed later.
Thereafter, formed is an ONO film which is a dielectric film between the floating gates and the control gates.
Next, a polycide film which is a material for the control gates is deposited and formed into control gates by reactive ion etching using a resist film patterned by photolithography as a mask.
Subsequently, after the resist film is removed, an impurity layer for isolating memory elements is formed using the control gates as a mask. Thereafter, an interlayer dielectric film, contact holes and metal interconnects are formed by known techniques.
However, in some cases, the top face of the embedded insulating film is desired to be higher than the surface of the semiconductor substrate. For example, in the case where the thickness of the element isolation film is required to be greater than the depth of trenches formed in the semiconductor substrate, the insulating film inevitably needs to be deposited to a thickness larger than the depth of the trenches formed in the semiconductor device. Or, in the case where trenches are not formed in the semiconductor substrate but the insulating film is embedded in recesses formed on the semiconductor substrate by patterning, it is preferable that the insulating film embedded in the recesses is formed to have a higher level than the top face of a stopper film patterned on the semiconductor substrate, for ensuring the thickness of the insulating film. Consequently, the insulating film deposited in the recesses connects to triangular or trapezoid oxide films on the stopper film. If a mask layer deposited in this state, a desired configuration cannot be obtained. Japanese Unexamined Patent Publication No. HEI 8(1996)-78389 limits the thickness of the insulating film embedded in the recesses to such that the top face of the insulating film embedded in the recesses is lower than the top face of the patterned stopper film on the semiconductor substrate. In this sense, the process of this publication is limited.
Furthermore, as this prior art, for depositing the insulating film so that the insulating film embedded in the recess will not connect to the triangular or trapezoid oxide films on the stopper film, it is necessary to increase a sputter component in HDP-CVD (the sputter component means a component sputtered by atoms of Ar, O
2
or the like; it is necessary to increase the sputter component and form a thin insulating film for separating the insulating film). Accordingly, the substrate and elements are more damaged. Further, a contact face of the stopper layer
5
and the mask layer
15
as shown in the prior art is so small that failures such as pinholes may take place.
Further, as regards fine traces of a patterned stopper film (in other words, in small active regions) which are surrounded by wide traces of the patterned stopper film (in other words, in large active regions) and separated from eac

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