Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-11
2001-07-03
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S276000, C438S303000, C438S586000
Reexamination Certificate
active
06255163
ABSTRACT:
TECHNICAL FIELD
The present invention regards a process for manufacturing selection transistors for nonvolatile serial-flash, EPROM, EEPROM and flash-EEPROM memories in standard or Alternate Metal Ground (AMG) configurations.
BACKGROUND OF THE INVENTION
As known, in nonvolatile memories of the above indicated type, even multilevel programmable ones, there is an N-channel selection transistor arranged in series with a memory element or with a bit line connected to a plurality of memory cells. In particular, in the case of serial-flash memories, the selection transistor acts as a selector for enabling or not enabling a memory array partition; in flash-EEPROM memories in AMG and standard configurations and in EPROM memories, the selection transistor belongs to the column decoder which allows the addressed column to be biased at set potentials.
In all the above cases, the selection transistor must have a good driving capability of the cells connected thereto. This characteristic is fundamental so as to avoid limitations on the output current of the selected memory cell. Any current limitations on the one hand reduce the operating window of the cells and on the other hand increase the operating times necessary to perform the different tests implemented in memory devices.
SUMMARY OF THE INVENTION
An advantage of the present invention is devising a manufacturing process that allows obtaining selection transistors with a better driving capability than those that may presently be obtained with standard processes.
According to embodiments of the present invention, a process is provided for manufacturing selection transistors for nonvolatile serial-flash, EPROM, EEPROM and flash-EEPROM memories in standard or AMG configurations that includes forming an N-channel selection transistor having gate, drain and source regions and implanting an N-type dopant alongside the gate region that is separate from the step that forms the source and drain regions. The invention also includes a nonvolatile memory formed by this process.
REFERENCES:
patent: 5140551 (1992-08-01), Chiu
patent: 5436478 (1995-07-01), Bergemont
patent: 5707884 (1998-01-01), Fontana et al.
patent: 5808937 (1998-09-01), Chi et al.
patent: 0926686-A1 (1999-06-01), None
Clementi Cesare
Cremonesi Carlo
Pio Federico
Zatelli Nicola
Anya Igwe U.
Galanthay Theodore E.
Iannucci Robert
Seed IP Law Group PLLC
Smith Matthew
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