Process for manufacturing MIS transistor with self-aligned...

Details Process for manufacturing MIS transistor with self-aligned... Process for manufacturing MIS transistor with self-aligned...

1999-06-28

2002-02-12

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S279000, C438S286000, C438S183000, C438S299000

Reexamination Certificate

active

06346450

ABSTRACT:

DESCRIPTION
1. Technical field
This invention relates to a MIS transistor with self-aligned grid and its manufacturing process. A MIS transistor is a transistor with a Metal-Insulator-Semiconductor type structure, for example such as MOS (Metal-Oxide-Semiconductor) transistors.
The invention is more particularly applicable to the manufacture of such transistors capable of operating in the hyper-frequency range, on a silicon substrate.
The invention is used for microelectronics applications for the manufacture of hyper-frequency and/or power circuits, for example for the production of circuits that can be used in the telecommunications field.
2. State of prior art
According to known art, hyper-frequency type components and circuits are made on gallium arsenide (AsGa) substrates, or on silicon (Si) substrates.
For cost reasons, circuits made on gallium arsenide substrates are usually not particularly complex and do not have a high integration density. Consequently the architecture of these circuits is not optimized for their compactness.
For example document (1), the reference of which is given at the end of this description, contains information about the production of hyper-frequency components on an AsGa substrate.
Furthermore,
FIG. 1
attached also contains an example of a hyper-frequency component, in fact a MOS (Metal Oxide Semiconductor) transistor made on a silicon substrate.
The transistor in
FIG. 1
comprises a source region
10
, a channel region
12
and a drain region
14
defined in a silicon substrate
16
. For example, the source and the drain are formed by implantation of n type or p type doping impurities and form regions with lower resistivity.
An insulating silicon oxide layer
18
is formed on the surface of substrate
16
and covers the source, channel and drain regions.
A non-through opening
20
is formed by etching in the oxide layer
18
approximately vertically in line with the channel region
12
. A thin oxide layer
22
at the bottom of opening
20
forms a grid insulation. Finally, a grid
24
is formed in the opening
20
.
The material in which the grid is formed, actually metal, has a low resistivity and thus enables high frequency operation of the resulting transistor.
The integration density of devices made according to
FIG. 1
depends on the precision with which the opening
20
, and then the grid
24
, are aligned with respect to the channel
12
and the source and drain regions
10
and
14
. This precision depends directly on the quality of manufacturing tools (particularly for alignment) used to make the semiconductor devices.
In a known manner, one way of increasing the compactness and integration density of circuits in order to make integrated circuits with MOS transistors on a silicon substrate, is to self-align the grid with respect to the source and drain regions.
It is assumed that the grid is self-aligned with respect to source and drain areas when the relative position of the grid and the source and drain areas are directly defined by the position of the grid itself, rather than being the result of an alignment of the means used (for example masks) to make these parts. In practice, self-alignment of the grid with respect to the source and drain regions is the result of a manufacturing process for the source and drain regions in which these regions are formed by implantation of impurities in the substrate using the grid, made earlier, as the implantation mask. The grid location thus precisely and automatically fixes the position of the source of the channel and the drain.
The processes for the formation of transistors with a grid self-aligned with the source and drain areas usually required a heat treatment carried out at high temperature. For example, in processes for making MOS on silicon transistors with a self-aligned grid, a heat treatment at a temperature of the order of 750° C. or more is carried out after implantation of impurities, in order to activate the source and drain areas.
Furthermore a densification or creep of the insulation placed between the grid and the first metal interconnection level is done within an approximately identical temperature range.
Furthermore, as mentioned above, a grid material with a low resistivity has to be used so that the transistor can operate at high frequency. For guidance, when hyper-frequency type devices are being made, in other words devices that usually operate at a frequency exceeding 36 MHz, the grid material used to make the transistors must preferably have a resistivity of between about 1 and 10 &mgr;&OHgr;·cm.
In fact, materials with a resistivity within the given range are incapable of resisting the temperatures of the heat treatments applied in the processes described for manufacturing transistors with self-aligned grid. In particular, these materials are not capable of resisting temperatures equal to or exceeding 750° C.
One material frequently used for making the grid for transistors with a self-aligned grid is polycrystalline silicon (poly Si). Polycrystalline silicon is capable of resisting the temperatures of heat treatments used when these transistors are being formed.
However, the resistivity of polycrystalline silicon is of the order of 10
3
&mgr;&OHgr;·cm, which is not compatible with envisaged applications of transistors in the hyper-frequency range. Furthermore, we do not know how to sufficiently reduce the resistivity of polycrystalline silicon so that transistors can operate in hyper-frequency.
Consequently, one purpose of this invention is to suggest a process for manufacturing MIS transistors with self-aligned grid, source and drain, and capable of operating within the hyper-frequency range.
Another purpose of the invention is to propose a process for manufacturing a compact transistor with interconnections in order to reduce the clearance of contacts with respect to the edge of grid conductors or interconnections.
Another purpose of the invention is to increase the integration density of the interconnections in a circuit comprising transistors with self-aligned grid, source and drain.
Another purpose of the invention is to propose a transistor designed to have a very high cutoff frequency.
Another purpose of the invention is to propose transistors compatible with the production of CMOS (complementary MOS) circuits with a high integration density.
DESCRIPTION OF THE INVENTION
More precisely, the purpose of the invention is a process for manufacturing MIS (Metal-Insulator-Semiconductor) transistors on a semiconductor substrate. The process is defined by claim
1
. Another purpose of the invention is a MOS transistor such as that defined in claim
23
.
The dummy grid made during the process performs two functions; initially, it is used to define the location of the source and drain regions in step b) and then to define the location of the final transistor grid made from a material with low resistivity. The coating of the dummy grid on its lateral flanks, after this dummy grid has been eliminated, forms a “mold” for the final grid.
These characteristics guarantee automatic and perfectly precise alignment of the final grid with respect to the source and drain regions.
The final grid is formed from one or several materials. Each of these materials is chosen so as to have a low resistivity. For example, the resistivity of the materials may be chosen within a range varying from 1 to 10 &mgr;&OHgr;·cm.
According to one particular aspect of the invention, step a) may comprise:
formation on the substrate of a stack comprising an oxide layer called the pedestal layer, a polycrystalline silicon layer and a silicon nitride layer in this order, and
forming of the stack by etching to form the dummy grid with lateral flanks.
In this embodiment of the process, the dummy grid is composed of a thin silicon oxide layer, a polycrystalline or amorphous silicon layer, and then a silicon nitride layer, in this order.
The silicon nitride layer may be beneficially used to form the side coating of the dummy grid.
According to one particular aspect of the invention, step c) comprises:

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