Process for manufacturing electronic devices having...

Details Process for manufacturing electronic devices having... Process for manufacturing electronic devices having...

1999-10-22

2003-06-03

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S593000

Reexamination Certificate

active

06573130

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors and salicidated-junction LV transistors.
BACKGROUND OF THE INVENTION
In advanced processes (gate lengths not exceeding 0.35 &mgr;m) the need has arisen to integrate EEPROM-type non-volatile memories in high-speed devices that use the technique of saliciding the diffusions. This technique is based on the use of a layer of “salicide” (self-aligned silicide) that reduces the resistivity of the junctions. The salicide layer (typically of titanium but also of cobalt or another transition metal) is formed by depositing a titanium layer on the entire device surface and carrying out a heat treatment phase that causes titanium to react with silicon, left bare on the junctions and the gate regions, so as to form titanium silicide. The unreacted titanium (that deposited on oxide regions for example) is then etched away using a suitable solution leaving titanium silicide intact. In this way both the gate regions and the junctions have in parallel a silicide layer of low resistivity (approx. 3-4&OHgr;/square) which enables the transistor series resistance to be reduced. The “salicide” technique is described, for example, in the article “Application of the self-aligned titanium silicide process to very large-scale integrated n-metal-oxide-semiconductor and complementary metal-oxidesemi-conductor technologies” by R. A. Haken in J. Vac. Sci. Technol. B, vol. 3, No. 6, November/December 1985.
The high voltages required for programming non-volatile memories (greater than 16 V) are, however, incompatible with saliciding the diffusions of the memory cells, since the breakdown voltage of salicidated junctions is less than 13 V.
Process flows permitting integration of non-volatile memory cells and high-speed transistors with salicidation have been investigated; however, this integration is difficult because these components have different characteristics and require different process steps.
SUMMARY OF THE INVENTION
The invention provides a process for manufacturing non-volatile cells and high-speed transistors with a small number of masks that is easy to implement and offers possible lower costs.


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Shiba and Kubota, “Downscaling of Floating-Gate EEPROM Modules for ASIC Applications,”Electroncis and Communications in Japan, Part 2 75(12), pp. 67-76, 1992.
Wolf, Stanley and Richard N. Tauber,Silicon Processing for the VLSI Era, vol. 3, Lattice Press, Sunset Beach, California, 1986, pp. 608-611.

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