Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-27
2003-12-02
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S222000, C438S416000, C438S421000, C438S422000
Reexamination Certificate
active
06656782
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to integrated circuits, and more particularly, to isolated-gate transistors (MOS transistors), especially those having an architecture of the substrate-on-insulator (SOI) type, produced on a thin silicon film isolated from the substrate by a thin insulating layer.
BACKGROUND OF THE INVENTION
The advantage of SOI type architectures is that they make transistors operate in a fully depleted mode, making it possible to considerably reduce the effects of short channels for technologies below 0.1 micron. In conventional processes for fabricating a substrate-on-insulator, the thickness of the thin silicon film (corresponding to the conduction channel of the transistor), which is isolated from the substrate by a thin insulating layer, cannot be reproducibly controlled and uncertainties on the order of 20 nm are found in the devices finally produced.
Moreover, at the present time the various substrate-on-insulator transistors produced in this way are mutually isolated laterally by isolation regions of the LOCOS (local oxidation of the substrate) type, which, as is well known to those skilled in the art, has regions in the form of a bird's beak. However, such lateral isolation encourages the appearance of large leakage currents and proves to be penalizing in terms of a footprint for the density of integration of the various transistors.
One approach is to produce lateral isolation regions of the shallow trench type, also well known to those skilled in the art, which are less penalizing with regard to leakage currents and to the density of integration. However, the production of such shallow trenches in a substrate-on-insulator proves destructive to the insulating film. Consequently, at the present time, production is limited to LOCOS type regions in substrates on an insulator.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of the invention is to produce transistors of the substrate-on-insulator type, with a silicon film and a buried dielectric which are very thin and have controlled thicknesses.
Another object of the invention is to produce these transistors between lateral isolation regions of the shallow trench type.
These and other objects, advantages and features of the invention are provided by a method of implementation that starts with a region of a substrate bounded laterally by lateral isolation regions of the shallow trench type. Then, a multilayer is formed on this substrate region. The multilayer is formed from a first layer comprising a silicon-germanium alloy surmounted by a second layer comprising silicon. The first layer of the multilayer will then be completely etched by selective etching and then filled with an insulating material. The source and drain regions and the channel region of the transistor will be produced in the second layer of the multilayer, and will thus be completely isolated vertically from the substrate by the layer of insulating material that has replaced the first layer of the multilayer. Moreover, the transistor thus produced will be isolated laterally from the other transistors by regions of the shallow trench type.
Furthermore, the invention has the advantage of producing the transistor without breaking the second layer of the multilayer within which the source, drain and channel regions are located. In other words, the continuity of this layer is preserved throughout the length of the process according to the invention. That is to say that there is in particular, at a given instant, no vertical etching of this layer followed by reforming of this layer, thereby making it possible to avoid the tricky technological problems of reconnecting the layer.
More generally, the invention provides a process for manufacturing an isolated-gate transistor comprising the formation, by selective epitaxy on the surface of an active region of a substrate bounded by a lateral isolation region of the shallow-trench type, of a multilayer comprising a first layer made of a silicon-germanium alloy surmounted by a silicon second layer. A gate oxide layer is formed on the multilayer, and a gate region is formed on the gate oxide layer and on the lateral isolation region.
The method further includes selectively etching the first layer of the multilayer so as to form a tunnel, and filling the tunnel with an insulating material.
The complete selective etching of the first layer of the multilayer is carried out from the edges of the lateral isolation region towards the gate. The step of selectively etching the first layer is advantageously preceded by a step of local deoxidation at the edges of the active region. The selective etching step is preferably carried out before the steps of implanting the source and drain regions. The thickness of the second layer may be on the order of tens of nanometers, for example, twenty nanometers.
The invention also provides an integrated circuit comprising an isolated-gate transistor, the source, drain and channel regions of which are produced in a silicon layer completely isolated vertically form a carrier substrate by an insulating layer and bounded laterally by a lateral isolation region of the shallow-trench type.
REFERENCES:
patent: 5955745 (1999-09-01), Yamazaki
patent: 6057214 (2000-05-01), Joyner
patent: 2795554 (2000-12-01), None
patent: 2795555 (2000-12-01), None
M.Jurczak, T. Skotnicki, M. Paoli, B. Tormen, J-L. Regolini, C. Morin, A. Schiltz, J. Martins, R. Pantel, and J. Galvier, “SON (Silicon On Nothing)—A New Device Architecture for the ULSI Era,” Digest Technical Papers, Symp. on VLSI Tech., (1999),pp. 29-30.*
M. Jurczak, T. Slotnicki, M. Paoli, B. Tormen, J.-L. Regolini, A Schlitz, J. Martins, R. Pantel, and J. Galvier, “SON (Silicon On Nothing)—A New Device Architecture for the ULSI Era,” Digest Tech. Papers, Symp. on VLSI Tech. (1999) pp. 29-30.*
MOS Transistors with Bottom-Isolated Source/Drain Regions, Research Disclosure, Kenneth Mason Publications, Hampshire, GB, No. 398, Jun. 1, 1997, pp. 378-379, XP000726504.
Jurczak et al, SON (Silicon on Nothing), A New Device Architecture for the ULSI Era, 1999 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Jun. 14-16, 1999, New York, 1999, pp. 29-30, XP000949338.
Monfray Stéphane
Skotnicki Thomas
Villaret Alexandre
Jorgenson Lisa K.
Magee Thomas
STMicroelectronics SA
Thomas Tom
LandOfFree
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