Process for manufacturing an integrated CMOS circuit

Details Process for manufacturing an integrated CMOS circuit Process for manufacturing an integrated CMOS circuit

1998-01-09

1999-03-16

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438 96, 438488, 438659, 438660, 438618, 438669, 438684, 257369, H01L 218238

Patent

active

058829652

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention is based on the problem of specifying an improved method for producing an integrated CMOS circuit using dual work function gate technology in which lateral dopant diffusion is suppressed and which can be carried out with reduced process complexity compared with known solutions.
2. Description of the Prior Art
Both n-channel MOS transistors and p-channel MOS transistors are used in CMOS logic circuits; for example, in inventors. Electrical connections between gate electrodes of p-channel MOS transistors and n-channel MOS transistors are, in this case, very often realized in a gate plane which is formed by structuring a layer and which comprises, in addition to the gate electrodes, connection elements between the gate electrodes. It is very often the case that the gate electrodes and the connection elements between the gate electrodes are formed as a continuous gate line. In CMOS circuits which are operated with a supply voltage of 5 volts, the gate structure is usually formed from n.sup.+ -doped polysilicon or polycide.
In CMOS circuits for low-voltage/low-power applications which are operated with a supply voltage of <3 volts, the MOS transistors are optimized such that they have threshold voltages .vertline.V.sub.th .vertline.<0.5 volt in conjunction with low leakage currents. The associated high requirements on the short-channel behavior of the MOS transistors are satisfied by the use of dual work function gate technology with an optimized gate work function. Dual work function gate technology is understood to mean the fact that the gate electrode of the n-channel MOS transistors is n.sup.+ -doped and the gate electrode of the p-channel MOS transistors is p.sup.+ -doped. Owing to this different doping in the gate electrodes for the n-channel MOS transistors and the p-channel MOS transistors, there is the risk of lateral dopant diffusion in the case of a gate structure having a continuous gate line which connects differently doped gate electrodes (see, for example, L. C. Parrillo, IEDM '85, p. 398).
The electrical properties, for example the threshold voltage V.sub.t h, of the MOS transistors depend on the gate doping. Lateral dopant diffusion leads to a change in the gate doping and thus to undesirable, uncontrollable parameter shifts. In the extreme case, it is possible for reverse doping of the gate electrodes to occur, and hence total failure of the components. Furthermore, in the connection between n.sup.+ -doped gate electrodes and p.sup.+ -doped gate electrodes, it is necessary, with regard to a low bulk resistance, that n.sup.+ -doped regions and p.sup.+ -doped regions adjoin one another directly since otherwise a space charge zone forms.
In order to suppress lateral dopant diffusion in dual work function gate technology, it has been proposed (see, for example, D. C. H. Yu et al., Int. J. High Speed Electronics and Systems, Vol. 5, p. 135, 1994) not to use any continuous connections made of polysilicon between differently doped gate electrodes in the gate plane. Instead, the gate line made of polysilicon is interrupted and is electrically conductively connected via a metal bridge made of aluminum, for example. As an alternative, after the interruption of the gate line, a suitable metallic conductor (TiN, WI WSi.sub.2) is deposited and structured. This solution is complicated and in some instances requires additional space for contact-making and metallization.
Furthermore, it has been proposed (see C. Y. Wong et al., IEDM '88, p. 238) to produce, in dual work function gate technology, planar source/drain regions and the correspondingly doped gate electrodes by implantation with the same dopant. For this purpose, the implantations are carried out before the structuring of the gate electrodes. With regard to planar source/drain regions, limitations must be observed in the case of the implantation doses and the thermal loading. However, this leads to a narrow process window; for example, during dopant activation in the

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patent: 5705845 (1998-01-01), Fujii
Takenaka et al. "High Mobility Poly-Si-TFTs Using Solid Phase Crystallized a-Si Films Deposited by Plasma Enhanced Chemical Vapor Deposition", Extended Abstracts of the 22.sup.22nd (1990 International) Conference on Solid State Devices and Materials, Sendai, 1990, pp. 955-958.
Lee et al. "New Robust n.sup.+ /p.sup.+ Dual-Gate CMOS Technology Optimized for Low Power Operation" International Journal of High Speed Electronics and Systems, vol. 5, No. 2 Jan. 1994 135-143.
Parrillo "Process and Device Consideration for Micron and Submicron CMOS Technology", Motorola, Inc. IEDM 85, 1985.
Wong et al. "Doping of N.sup.+ and P.sup.+ Polysilicon in a Dual-Gate CMOS Process" IBM Research Division, T.J. Watson Research Center, 1988.
Seiichi, Patent Abstracts of Japan, Publication No. JP7302844, Publicaton Date Nov. 14, 1995, "Dual Gate Structured Complementary MIS Semiconductor Device".
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