Process for manufacturing an integrated circuit comprising an ar

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438238, H01L 218247

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active

059769335

ABSTRACT:
A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming rows (3) of the memory cell array (1), and outside the memory cell array area defining second strips (17) of the second layer of conductive material (11) for forming interconnection lines (100) for electrically interconnecting the rows (3) of the memory cell array with a circuitry (5,RD) said, first strips (22) and the second strips (17) of the second layer of conductive material (11) are automatically joined at respective ends thereof at said boundary region.

REFERENCES:
patent: 5013674 (1991-05-01), Bergemount
patent: 5538912 (1996-07-01), Kunorl et al.
patent: 5716864 (1998-02-01), Abe
European Search Report from European application No. 97830359, filed Jul. 16, 1997.
Patent Abstracts of Japan, vol. 016, No. 240 (E-1211), Jun. 3, 1992 & JP 04 049675, Feb. 19, 1992.
Patent Abstracts of Japan, vol. 097, No. 003, Mar. 31, 1997 & JP 08 298314, Nov. 12, 1996.

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