Process for manufacturing an EEPROM having a peripheral transist

Details Process for manufacturing an EEPROM having a peripheral transist Process for manufacturing an EEPROM having a peripheral transist

1997-04-28

2000-12-05

Dutton, Brian

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438201, 438211, 438216, 438257, 438266, 257324, 257326, H01L 218238, H01L 21336, H01L 29792

Patent

active

061566101

ABSTRACT:
A process for manufacturing an integrated circuit provides for the formation of a matrix of floating-gate non-volatile memory cells having dual polysilicon levels, with the two polysilicon levels being isolated by a gate dielectric layer (4) and an interpoly dielectric layer (9) therebetween, and for the concurrent formation of one type of thick-oxide transistor (21) having an active area (7) in regions peripheral to the matrix. The process of the invention provides for removal, during the step of defining the first-level polysilicon (5), the polysilicon (5) from the active area (7) of the thick-oxide transistor (21), so that the gate oxide of the transistor (21) results from the superposition of the first (4) and second (9) dielectric layers.

REFERENCES:
patent: 5104819 (1992-04-01), Freiberger et al.

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