Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-09-22
2000-03-28
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438222, 438223, 438224, 438226, 438227, H01L 21336, H01L 218234
Patent
active
060431148
ABSTRACT:
Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.
REFERENCES:
patent: 3974003 (1976-08-01), Zirinsky et al.
patent: 4005453 (1977-01-01), Le Can et al.
patent: 4477310 (1984-10-01), Park et al.
patent: 4525920 (1985-07-01), Jacobs et al.
patent: 4564416 (1986-01-01), Homma et al.
patent: 4578128 (1986-03-01), Mundt et al.
patent: 4622082 (1986-11-01), Dyson et al.
patent: 4684971 (1987-08-01), Payne et al.
patent: 4717686 (1988-01-01), Jacobs et al.
patent: 4766090 (1988-08-01), Coquin et al.
patent: 4803179 (1989-02-01), Neppl et al.
patent: 4943536 (1990-07-01), Havemann
patent: 5216269 (1993-06-01), Middelhoek et al.
patent: 5237188 (1993-08-01), Iwai et al.
patent: 5396093 (1995-03-01), Lu
patent: 5508540 (1996-04-01), Ikeda et al.
patent: 5508549 (1996-04-01), Watanabe et al.
Wolf, S., "Silicon Processing for the VLSI Era vol. 1," pp. 64-65, 1986.
Ghandhi, S., "VSLI Fabrication Principles Silicon and Gallium Arsenide," pp. 735-738, 1994.
Yamaguchi et al, "Process integration and device performance of a submicrometer BiCMOS with 16-GHz f(t) double Poly-Bipolar devices," IEEE Transactions on Electron Devices, vol. 36, No. 5 pp. 890-896, May 1989.
Arakawa Hisashi
Kawagoe Hiroto
Kitano Manabu
Kiyota Shogo
Naganuma Takashi
Hack Jonathan
Hitachi , Ltd.
Niebling John F.
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