Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-31
2003-11-18
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S253000
Reexamination Certificate
active
06649465
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a process for manufacturing the same. More particularly, the invention relates to a technique that is effectively applicable to a structure for forming an information storing capacitive element having an MIM (Metal-Insulator-Metal) structure, in an aperture (a recess) formed in an insulating film, and also to a process for manufacturing the element.
A DRAM has a memory cell selecting MISFET and an information storing capacitive element connected in series to this MISFET. The information storing capacitive element is formed, for example, by depositing a silicon film constituting a lower electrode, and a tantalum oxide film constituting a capacitive insulating film, and a silicon film constituting an upper electrode in this order.
Further, the information storing capacitive element is formed in the aperture formed deeply in the insulating film in order to achieve fineness thereof and attain a desired capacitance.
SUMMARY OF THE INVENTION
However, the lower electrode made of silicon needs to be subjected to heat treatment (in oxidizing atmosphere, at 800° C., for 3 minutes) in order to improve crystallization and film quality of tantalum oxide formed on an upper layer thereof. During the heat treatment, a silicon nitride film is formed at an interface between the silicon film and the tantalum oxide film. Consequently, the tantalum oxide film and the silicon nitride film act as dielectric members. Although leakage current flowing therethrough can be reduced, a large dielectric constant thereof is difficult to be achieved.
The smaller the element becomes, the smaller the diameter of the aperture in which the information storage capacitive element is formed becomes further. As the diameter of the aperture decreases, silicon films crystallized on an inner uneven surface of the aperture are in contact with one another. Consequently, it is no longer possible to form an upper layer of the tantalum oxide or the like.
Inventors of the present invention have studied and developed materials for a lower electrode constituting an information storing capacitive element. To solve the above-mentioned problem, they have proposed that ruthenium (Ru) may be used as materials of the lower electrode.
This Ruthenium is thought to generate no film having a small dielectric constant such as an oxynitriding film, and to be capable of being formed thin because the ruthenium is metal.
However, the inventors have studied use of a Ru film as a lower electrode, and consequently found drawbacks of leakage current and electric contact failure and the like.
The inventors have hard studied these drawbacks, and consequently thought that the leakage current flows for the following reasons.
As will be described later in detail, a Ru film is formed by reacting a Ru organic compound with an oxidizer. Due to this, organic substances and oxygen are taken in the Ru film. As a result, the Ru film is poor in fineness and has unevenness on a surface thereof.
Over such the Ru film, a capacitive insulating film of a tantalum oxide film or the like may be formed, and heat treatment may then be performed to crystallize the tantalum oxide and improve a quality of the film thereof. By this, the Ru film shrinks and changes, and thereby causes the tantalum oxide film of an upper layer thereof to be deformed. As a result, the leakage current is thought to flow therethrough.
Further, regarding the electric contact failure, this is probably because the oxygen in the Ru film diffuses into a plug for connecting a memory cell selecting MISFET and the Ru film (a lower electrode of the information storing capacitive element), and thereby an oxide (an insulating substance) is formed over a surface of this plug.
An object of the present invention is to provide a technique of forming a Ru film constituting a lower electrode of an information storage capacitive element, in an aperture, with high precision.
Another object of the invention is to provide a technique of forming a Ru film with high quality, and thereby of improving a characteristic of a capacitive insulating film formed thereon and further improving a characteristic of the information storing capacitive element.
The above-mentioned and the other objects and the novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.
Of inventions disclosed in the present application, representative inventions will be described as follows.
1. According to the present invention, a process for manufacturing a semiconductor integrated circuit device comprises the steps of: (a) forming a memory cell selecting MISFET over a major surface of a semiconductor substrate; (b) forming a plug electrically connected to a source and drain region of said memory cell selecting MISFET; (c) forming a silicon oxide film on said plug; (d) forming an aperture arriving at a surface of said plug, in said silicon oxide film; (e) repeating deposition of a Ru film and performance of heat treatment and thereby forming a laminating film of a Ru film on a side wall and a bottom portion of said aperture; (f) forming a capacitive insulating film over said laminating film of a Ru film; and (g) forming an upper electrode on said capacitive insulating film.
2. Said performance of heat treatment includes heat treatment performed in reducing atmosphere.
3. And, according to the present invention, a process for manufacturing a semiconductor integrated circuit device comprises the steps of: (a) forming a memory cell selecting MISFET over a major surface of a semiconductor substrate; (b) forming a plug electrically connected to a source and drain region of said memory cell selecting MISFET; (c) forming a silicon oxide film on said plug; (d) forming an aperture arriving at a surface of said plug, in said silicon oxide film; (e) making an organic compound of Ru react with an oxidizer and thereby forming a Ru film on a side wall and a bottom portion of said aperture; (f) heat-treating said Ru film in reducing atmosphere; (g) forming a capacitive insulating film over said Ru film; and (h) forming an upper electrode over said capacitive insulating film.
4. And, according to the present invention, a process for manufacturing a semiconductor integrated circuit device comprises the steps of: (a) forming a memory cell selecting MISFET over a major surface of a semiconductor substrate; (b) forming a plug electrically connected to a source and drain region of said memory cell selecting MISFET; (c) forming a silicon oxide film on said plug; (d) forming an aperture arriving at a surface of said plug, in said silicon oxide film; (e) making an organic compound of Ru react with an oxidizer and thereby forming a Ru film on a side wall and a bottom portion of said aperture; (f) performing first heat treatment in reducing atmosphere and second heat treatment in non-oxidizing atmosphere at said Ru film; (g) forming a capacitive insulating film over said Ru film; and (h) forming an upper electrode over said capacitive insulating film.
5. A semiconductor integrated circuit device that is the present invention comprises: (a) a memory cell selecting MISFET formed over a major surface of a semiconductor substrate; (b) a plug electrically connected to a source and drain region of said memory cell selecting MISFET; (c) a silicon oxide film formed on said plug; (d) an aperture provided in said silicon oxide film and extending up to a surface of said plug, and having a depth five times longer than a short diameter thereof; and (e) an information storing capacitive element having a lower electrode formed in said aperture and composed of a laminating film of a Ru film formed by a CVD method, and a capacitive insulating film formed on said lower electrode, and an upper electrode formed over said capacitive insulating film.
REFERENCES:
patent: 6060735 (2000-05-01), Izuha et al.
patent: 6306667 (2001-10-01), Arita et al.
patent: 6399399 (2002-06-01), Yamamoto
patent: 2001/0031527 (2
Iijima Shinpei
Yamamoto Satoshi
Hitachi , Ltd.
Nguyen Tuan H.
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