Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-10-03
2006-10-03
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S593000, C257S314000, C257S316000, C257SE21679, C257SE27103
Reexamination Certificate
active
07115472
ABSTRACT:
A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an “L” shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.
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Brambilla Claudio
Caprara Paolo
Cereda Manlio Sergio
Graybeal Jackson Haley LLP
Jorgenson Lisa K.
Le Dung A.
Santarelli Bryan A.
STMicroelectronics S.r.l.
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