Electronic digital logic circuitry – Significant integrated structure – layout – or layout...
Reexamination Certificate
2011-08-23
2011-08-23
Cho, James (Department: 2819)
Electronic digital logic circuitry
Significant integrated structure, layout, or layout...
C716S055000
Reexamination Certificate
active
08004315
ABSTRACT:
The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient implementation of logic circuitry, with a dramatic reduction in the pattern complexity (or number of unique layout patterns at each mask level) for realistically sized designs. This reduction in pattern complexity that the invention provides is particularly important for advanced and emerging semiconductor processes, because it enables effective use of SMO and full-chip mask optimization.
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Cho James
Garrod David
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