Process for making a semiconductor device using partial etching

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S706000, C438S745000, C257SE21396

Reexamination Certificate

active

07910442

ABSTRACT:
A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.

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patent: 7494859 (2009-02-01), Cho et al.
patent: 2005/0101113 (2005-05-01), Brask et al.
patent: 2007/0052037 (2007-03-01), Luan
patent: 2005048334 (2005-05-01), None
S.B. Samavedam, et al., “Dual-Metal Gate CMOS with HfO2 Gate Dielectric,” Electron Devices Meeting, 2002. IEDM '02. Digest. International Dec. 8-11, 2002 pp. 433-436.
S.C. Song, et al., “Highly Manufacturable 45nm LSTP CMOSFETs Using Movel Dual High-k and Dual Metal Gate CMOS Integration,” Symposium on VLSI Technology Digest of Technical Papers, 2006.

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