Process for isolating an exposed conducting surface

Details Process for isolating an exposed conducting surface Process for isolating an exposed conducting surface

2000-05-18

2003-04-08

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S635000, C438S680000, C438S687000, C438S688000, C438S768000

Reexamination Certificate

active

06544886

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of semiconductor devices and more specifically to isolating exposed conducting surfaces in semiconductor devices.
BACKGROUND OF THE INVENTION
As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects. Unfortunately, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.
In a conventional interconnect process, the aluminum (and any barrier metals) are deposited, patterned, and etched to form the interconnect lines. Then, an intrametal dielectric (IMD) is deposited and planarized. In a damascene process, the IMD is formed first. The IMD is then patterned and etched. The barrier layer and a copper seed layer are then deposited over the structure. The copper layer is the formed using the seed layer over the entire structure. The copper is then chemically-mechanically polished (CMP'd) to remove the copper from over the IMD
16
, leaving copper interconnect lines
18
as shown in
FIG. 1A. A
metal etch is thereby avoided.
Next, a silicon nitride layer
20
is deposited over the copper
18
and IMD
16
, as shown in FIG.
1
B. Copper must be surrounded by a barrier to prevent it from diffusing into the surrounding dielectric. An interlevel dielectric (ILD)
22
is then formed over the silicon nitride layer
20
. Unfortunately, the silicon nitride layer increases the line-to-line capacitance by increasing the total effective dielectric constant of the interievel dielectric (ILD
22
and silicon nitride
20
). Silicon nitride
20
also takes up voluble space that is needed for other essential device components.
SUMMARY OF THE INVENTION
The invention forms a thin aluminum-oxide on the surface of an exposed conducting surface. A selective aluminum deposition is used to deposit aluminum only on the conducting surface and not on the surrounding dielectric. The aluminum is then oxidized to form an isolation layer.
An advantage of the invention is providing an isolating film on a conducting surface but not a surrounding dielectric to minimize the space taken by the isolating film and/or reduce the effective dielectric constant.
This other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.


REFERENCES:
patent: 5252517 (1993-10-01), Blalock et al.
patent: 5547901 (1996-08-01), Kim et al.
patent: 5627102 (1997-05-01), Shinriki et al.
patent: 5659127 (1997-08-01), Shie et al.
patent: 5766379 (1998-06-01), Lanford et al.
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5936293 (1999-08-01), Parkin

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