Process for integrating a MOS logic device and a MOS memory devi

Details Process for integrating a MOS logic device and a MOS memory devi Process for integrating a MOS logic device and a MOS memory devi

1998-05-07

1999-12-21

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438258, 438592, 438952, H01L 218242, H01L 21336, H01L 213205, H01L 214763

Patent

active

060048433

ABSTRACT:
A method for fabricating both MOS memory devices, and MOS logic devices, on a single silicon chip, has been developed. The process features combining process steps for both device types, however using a self-aligned contact structure, in the MOS memory device region, for purposes of increasing device density, while using metal silicide regions, only in MOS logic device regions, for purposes of improving device performance. An organic coating protects MOS memory devices, from procedures used to remove insulator layers from silicon surfaces of MOS logic devices, prior to the formation of the self-aligned silicide regions, on the exposed silicon surfaces, in MOS logic device regions.

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patent: 5605853 (1997-02-01), Yoo et al.
patent: 5612238 (1997-03-01), Sato et al.
patent: 5691235 (1997-11-01), Meikle et al.

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