Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-19
2003-05-06
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000, C438S648000, C438S666000, C438S672000, C438S685000
Reexamination Certificate
active
06559050
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor integrated circuits and, more particularly, to the conducting plugs that provide a conducting path through the insulating layer in an integrated circuit.
2. Description of the Prior Art
As the sub-quarter micron complementary metal oxide semiconductor devices have been developed, many promising approaches require conducting plugs to withstand higher temperatures than are necessary for prior art devices. In particular, the conducting plugs have typically used a titanium/titanium nitride interface to increase the cohesion of the conducting plug to the substrate and to provide a diffusion barrier.
Referring to
FIG. 1
, the preliminary steps in forming a conducting plug according to the prior art is shown. A dielectric layer
11
is formed over a silicon substrate
10
. A via
13
is formed in the dielectric layer
11
, the via extending the substrate
10
. A titanium/titanium nitride layer
12
is formed over the surface of the dielectric
11
, the walls of the via
13
, and the exposed substrate
10
surface. A tungsten layer
14
is formed over the exposed surface of titanium/titanium nitride layer
12
in sufficient depth to fill the via
13
. In process steps not illustrated, the tungsten layer
14
and the titanium/titanium nitride layer
12
are planarized, thereby providing a surface consisting of the dielectric
11
region and an exposed tungsten plug
13
.
Without the titanium/titanium nitride layer
12
, the mechanical coupling, and therefore the electrical coupling between the tungsten
13
and the silicon substrate is found to be unsatisfactory. The titanium/titanium nitride layer also provides a barrier for the diffusion of tungsten into the substrate. While the titanium/titanium nitride layer
12
provides a satisfactory solution to the mechanical/electrical coupling between the tungsten
13
and the silicon substrate
10
, this solution results in other problems. For example, forming the titanium/titanium nitride layer requires an additional deposition chamber. In addition, the structure is not thermally stable at the 850° C. temperatures that are required for annealing of the contact bitline structure.
A need has been felt for a contact/conducting plug structure that can withstand the high temperatures required to form bitline and capacitor integrated circuit elements while providing a relatively low resistivity.
SUMMARY OF THE INVENTION
The aforementioned and other features are accomplished, according to the present invention, by creating a tungsten conducting plug with a tungsten-silicon-nitride (WSi
Y
N
Z
) interface between the tungsten plug and the silicon substrate. After forming a via in the dielectric layer, the via exposing a portion of the silicon substrate, a nitrided surface layer is formed on the exposed dielectric layer and silicon layer surfaces. Then a layer of tungsten, tungsten nitride, or a mixture thereof is formed wherein the via is now filled. An annealing process removes the nitrogen in the conducting plug, but leaves a tungsten-silicon-nitride contact/barrier region between the tungsten plug and the silicon substrate. In another embodiment, a thin silicon layer is formed on the exposed dielectric layer and silicon layer surfaces prior to the formation of the nitrided surface layer. In another embodiment, a thin layer of tungsten nitride is formed over the nitrided layer covering the exposed dielectric layer and silicon layer surfaces. Thereafter, a layer of tungsten is formed, a layer that fills the via, prior to the annealing step.
These and other features of the present invention will be understood upon the reading of the following description in conjunction with the Figures.
REFERENCES:
patent: 4994410 (1991-02-01), Sun et al.
patent: 5066615 (1991-11-01), Brady et al.
patent: 5899741 (1999-05-01), Tseng et al.
patent: 5913145 (1999-06-01), Lu et al.
patent: 6025264 (2000-02-01), Yew et al.
patent: 6147000 (2000-11-01), You et al.
patent: 6221792 (2001-04-01), Yang et al.
Anderson Dirk N.
Hwang Ming-Jang
Lee Wei
Lu Jiong-Ping
McKee William R.
Brady III W. James
Garner Jacqueline J.
Picardat Kevin M.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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