Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-09
2002-11-05
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S299000, C438S303000, C438S585000, C438S595000
Reexamination Certificate
active
06475842
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a method of manufacturing a semiconductor device and, more specifically, to a method of manufacturing a transistor device including a gate oxide, wherein the gate oxide side-wall is protected from plasma damage during formation.
BACKGROUND OF THE INVENTION
It is well known that microcircuit fabrication requires the formation of precisely defined active devices, such as transistor poly gates and transistor gate oxides, which are subsequently interconnected to create components and very large scale integration (VLSI) or ultra large scale integration (ULSI) circuits. Equally well known is that the patterns defining the width of such devices are typically created by optical lithographic processes that involve the use of a mask and radiation, such as ultraviolet light, electron beams, or x-rays for a positive photoresist, to expose a pattern in the photoresist material. The exposed patterns in the photoresist are formed when the wafer undergoes the radiation exposure. The exposed portion of the photoresist is then removed and unexposed portions of the photoresist remains to protect the substrate regions that it covers. Locations from which photoresist has been removed can then be subjected to a variety of subsequent processing steps.
Currently, transistor device formation involves a plasma etch step applied to the areas of the substrate layer left uncovered by the previous photoresist exposure and removal step described above. Typically the plasma etch is applied to remove only the poly gate layer; however, present etch technology is unable to accurately time the etch to remove all of the poly gate material without removing any of the gate oxide material. Thus, in an effort to appropriately remove all of the poly gate material, the poly gate is over etched, typically by about 10% of the poly gate thickness. However, as metal-oxide-semiconductor (MOS) technology continues to advance and the features of the MOS devices shrink, a scaling down in the vertical dimension of the gate oxide also occurs. The 10% overetch becomes substantial because typical gate oxide thicknesses are approaching 2.0 nm and below. For instance, if a poly gate having a thickness of 100 nm is over etched by 10%, i.e., 10 nm, the gate oxide having a 2.0 nm thickness is being completely etched, which results in damage to both the sidewall and the silicon substrate.
Removing portions of the gate oxide using the plasma etch is undesirable, because damage to the side-wall of the gate oxide might occur. The damage typically occurs when the ionic component of the plasma etch comes into contact with the side-wall of the gate oxide, causing traps to build up in the damaged side-wall of the gate oxide, which leads to easier hot carrier formation and deterioration of the gate oxide integrity during subsequent manufacturing steps and operation. Moreover, if the plasma etch contacts the silicon substrate, it might cause channel mobility degradation, gate oxide quality degradation and short hot carrier lifetime.
Accordingly, what is needed in the art is a method of manufacturing a semiconductor device, and more specifically a transistor device having a gate oxide, that does not experience the gate oxide problems associated with the prior art methods for manufacturing the transistor devices.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a method for manufacturing a semiconductor device. The method includes forming an oxidized portion of an initial gate structure and a sacrificial gate layer, and further includes removing the oxidized portion of the initial gate structure and the sacrificial gate layer to form a transistor device. In an exemplary embodiment, the method further includes subjecting a patterned gate layer to an etch to form the initial gate structure and the sacrificial layer. In an advantageous embodiment, the gate layer is patterned having a width greater than a predetermined design width.
Thus, in an advantageous aspect of the present invention, a transistor is manufactured, including a gate and a gate oxide. Moreover, the gate oxide is manufactured such that the gate oxide sidewall is protected from plasma damage, resulting in a highly reliable gate dielectric, without encountering the problems associated with the prior art methods.
In one illustrative embodiment, the patterned gate layer is subjected to a plasma etch. Furthermore, in another illustrative embodiment, the oxidized portion is removed using a non-plasma etch, for example a chemical etch using hydrogen fluoride. The oxidized portion in an exemplary embodiment has a thickness ranging from about 1 nm to about 5 nm. By removing the oxidized portions, in an advantageous embodiment a gate is formed, including oxide spacers located adjacent the gate.
Another aspect of the present invention provides a semiconductor device manufactured using the method described above and a method of manufacturing an integrated circuit. The method of manufacturing an integrated circuit includes (1) forming transistors as described above, and (2) forming interconnects to connect the transistors to form an integrated circuit.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 4837180 (1989-06-01), Chao
patent: 5075241 (1991-12-01), Spratt et al.
patent: 5776821 (1998-07-01), Haskell et al.
patent: 5856227 (1999-01-01), Yu et al.
Cheah Kean Syn
Low Hooi Peng
Ma Yi
Agere Systems Inc.
Lytle Craig P.
Smith Matthew
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