Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-09
2001-04-10
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S138000, C438S274000, C438S302000, C438S303000, C438S304000, C438S305000, C257S344000
Reexamination Certificate
active
06214673
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to semiconductor device and, more particularly, to a process for forming a vertical DMOS device having increased source contact area.
BACKGROUND OF THE INVENTION
Davies, U.S. Pat. No. 4,960,723, describes a method for making a self-aligned vertical field effect transistor wherein a silicon nitride sidewall spacer is formed around a polysilicon gate and an oxide spacer is formed covering the nitride sidewall spacer. Using the oxide spacer as a mask, a portion of the source is etched to expose a portion of the silicon substrate, following which the oxide spacer is removed. The contact area between the source and source electrode is thereby increased.
Lin, U.S. Pat. No. 5,498,555, discloses a method for making a horizontal FET having first spacer elements of polysilicon on the vertical sidewalls of the gate electrode and second spacer elements of silicon dioxide on the first spacer elements, the intent being to improve performance and provide immunity against hot carrier effects.
Su et al., U.S. Pat. No. 5,208,472, discloses a horizontal MOS device having two layers of dielectric film on the edge of the gate; the device is intended to have low junction leakage and reduced shorting from gate to source/drain.
Blanchard, U.S. Pat. No. 5,663,079, describes a method of making MOS-gated, double diffused semiconductor devices. In one embodiment, a nitride spacer layer is used to separate an implanted and diffused deep body region from the gate region, then removed by etching.
Lin, U.S. Pat. No. 5,668,065, discloses a process for simultaneously forming silicide-based self-aligned contacts and local interconnects in a horizontal semiconductor device. Oxide spacers adjacent the gate provide a lightly doped drain region within the drain region adjacent the gate and also isolate the gate from a subsequently formed self-aligned source region contact.
Tsai et al., U.S. Pat. No. 5,702,972, describes a method of reducing source/drain resistance in the fabrication of a horizontal semiconductor device, wherein first spacers of oxide are formed on the sidewalls of the gate electrode, and second spacers of nitride are formed on the first spacers. Following implanting of heavily doped source/drain regions, the second spacers are removed.
The disclosures of the just discussed six patents are incorporated herein by reference.
SUMMARY OF THE INVENTION
In accordance with the present invention, a process for forming a vertical semiconductor device having increased source contact area comprises: forming on a silicon substrate a gate that comprises a layer of polysilicon deposited on a layer of oxide, and implanting and driving a dopant of a first conductivity type into the substrate to form a well region in the substrate. A dopant of a second conductivity type is implanted and driven into the well region, thereby forming a shallow source region in the well region, and a first layer of oxide is deposited over the gate and over the source and well regions in the substrate. The first oxide layer is etched to form a first spacer of oxide on the substrate adjacent the gate.
A thin layer of nitride is deposited over the gate and over the source region in the substrate, and a second layer of oxide is deposited over the thin nitride layer. The second layer of oxide is etched to form a second spacer of oxide that is separated from the first oxide spacer and the substrate by the thin nitride layer. Using the oxide and nitride spacers as a mask, the polysilicon layer in the gate and the source region in the substrate are selectively etched to remove the thin nitride layer from the gate and substrate, a portion of the gate polysilicon layer, and a portion of the source region, thereby forming in the source region a recessed portion that comprises substantially vertical and horizontal surfaces.
A dopant of a first conductivity type is implanted and driven into the recessed portion of the source region, thereby forming a shallow emitter region in the well region underlying the recessed portion of the source region. The second oxide spacer and the thin nitride layer separating it from the first oxide spacer are removed by etching, and a layer of conductive material is deposited on the remaining polysilicon layer and on the source region, whose recessed portion provides increased contact area with the conductive material.
Further in accordance with the present invention, a process for forming a vertical semiconductor device having increased source contact area comprises: forming on a silicon substrate a gate that comprises a layer of polysilicon deposited on a layer of oxide, and implanting and driving a dopant of a first conductivity type into the substrate to form a well region in the substrate. A dopant of a second conductivity type is implanted and driven into the well region, thereby forming a shallow source region in the well region, and a layer of oxide is deposited over the gate and over the source and well regions in the substrate. The oxide layer is etched to form a first spacer of oxide on the substrate adjacent the gate.
A layer of nitride is deposited over the gate and over the source region in the substrate and etched to form a spacer of nitride adjacent the oxide spacer. Using the oxide and nitride spacers as a mask, the polysilicon layer in the gate and the source region in the substrate are selectively etched to remove a portion of the gate polysilicon layer and a portion of the source region, thereby forming in the source region a recessed portion that comprises substantially vertical and horizontal surfaces.
A dopant of a first conductivity type is implanted and driven into the recessed portion of the source region, thereby forming a shallow emitter region in the well region underlying the recessed portion of the source region. The nitride spacer is removed by etching, and a layer of conductive material is deposited on the remaining polysilicon layer and on the source region, whose recessed portion provides increased contact area with the conductive material.
The highly doped source region in the vertical semiconductor device made by the process of the present invention is characterized by increased source contact area that includes vertical and horizontal components and enables improved I-off capability.
REFERENCES:
patent: 4960723 (1990-10-01), Davies
patent: 5130272 (1992-07-01), Ferla et al.
patent: 5155052 (1992-10-01), Davies
patent: 5208472 (1993-05-01), Su et al.
patent: 5498555 (1996-03-01), Lin
patent: 5663079 (1997-09-01), Blanchard
patent: 5668065 (1997-09-01), Lin
patent: 5702972 (1997-12-01), Tsai et al.
Grebs Thomas Eugene
Trost Jason Richard
Bowers Charles
Intersil Corporation
Jaeckle Fleischmann & Mugel
Sarkar Asok K.
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