Process for forming ultra-shallow source/drain extensions

Details Process for forming ultra-shallow source/drain extensions Process for forming ultra-shallow source/drain extensions

1999-02-22

2001-02-06

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S595000

Reexamination Certificate

active

06184097

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with ultra-shallow source and drain extensions.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (e.g., boron) or an N-type dopant (e.g., phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-inducted barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form deeper source and drain regions and shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a thermal diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions, as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions, which are necessary for proper silicidation. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source and drain extensions have become more difficult to manufacture. For example, smaller transistors should have ultra-shallow source and drain extensions with less than 30 nanometer (nm) junction depth. Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation and diffusion doping techniques are susceptible to channeling effects, which form a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects or crystal defects generated in the bulk semiconductor substrate during ion implantation can cause undesirable transient enhanced diffusion (TED) of the dopant during subsequent thermal processes. The diffusion often extends the source and drain extensions vertically into the bulk semiconductor substrate.
Thus, there is a need for a method of manufacturing ultra-shallow source and drain extensions that is not susceptible to transient enhanced diffusion. Further still, there is a need for transistors that have ultra-shallow junction source and drain extensions. Even further still, there is a need for an efficient method of manufacturing source and drain extensions.
SUMMARY OF THE INVENTION
The present invention relates to a method of manufacturing an integrated circuit. The method includes providing a gate structures, including a dummy spacer material from a portion of the substrate, removing the dummy spacer material, forming an amorphous region in the portion of the substrate, and providing dopants to the amorphous region to form an extension to a source or a drain. Removing the dummy spacer material leaves an opening. The amorphous region is formed in a substrate below the opening, and dopants are provided through the opening.
The present invention further relates to a method of manufacturing an ultra-large scale integrated circuit. The circuit includes a plurality of field effect transistors having shallow source and drain extensions. The method includes steps of removing a dummy spacer material from at least part of a gate structure on a top surface of a semiconductor substrate to form a first hole and a second hole, providing a semiconductor implant through the first hole and through the second hole, and providing a dopant implant through the first hole and through the second hole. The dummy spacer material is provided as part of the gate structure.
The present invention further relates to a process for forming shallow source extensions and shallow drain extensions in a semiconductor substrate. The process includes forming a plurality of gate structures on a top surface of the substrate, removing a pair of spacers from each of the gate structures, thereby exposing the top surface of the substrate, and providing a dopant through the exposed top surface of the substrate. The dopant creates the shallow source extension and the shallow drain extension.


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