Process for forming slots of different types in self-aligned rel

Details Process for forming slots of different types in self-aligned rel Process for forming slots of different types in self-aligned rel

1984-02-03

1986-04-01

Kittle, John E.

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

430314, 430315, 430316, 430317, 430323, 430324, 430394, 156648, 156650, 1566571, 156662, G03C 500, H01L 21306

Patent

active

045798125

ABSTRACT:
Slots of different types are fabricated using a single latent image mask. The slots of different types are thus located with respect to each other in a self-aligned relationship. In one embodiment an oxide of the semiconductor material, e.g., silicon dioxide, is used as a unitary masking layer. The slots of various types are defined in the mask and are fabricated in succession by relying on a universal etch and differential thicknesses for the oxide layers over slots of the different types. When the slots are formed they are filled with a suitable material. In another embodiment at least a dual layer latent image mask is used in which the two materials have different etch properties. One layer is used as a stop etch layer during fabrication of one of the slot types.

REFERENCES:
patent: 3542551 (1970-11-01), Rice
Betz et al., "Self-Aligned Contact Holes", IBM Technical Disclosure Bulletin, v. 24, No. 9, Feb. 1982, pp. 4643-4644.
Magdo et al., "Self-Aligned ROI to SAM Structure", IBM Technical Disclosure Bull., vol. 24, No. 10, Mar. 1982, pp. 5115-5118.
Malaviya, "Self-Aligned Deep Trench Isolation for Bipolar Transistors", IBM Tech. Disclosure Bull., vol. 25(5), Oct. 1982, pp. 2292-2293.
Ephrath, "Reactive Ion Etching for VLSI", IEEE Transactions on Electron Devices, v. ED-28(11), Nov. 1981, p. 1315-1319.
Wang et al., "Reactive-Ion Etching Eases Restrictions on Materials and Feature Sizes", Electronics, Nov. 1983, pp. 157-161.
Kendall, "Vertical Etching of Silicon at Very High Aspect Ratios", Annual Review of Material Science, vol. 9, 1979, pp. 373-403.
Minegishi et al., "A Submicron CMOS Megabit Level Dynamic RAM Technology Using a DFTC Cell", Proceedings IEDM, 1983, pp. 319-322.

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