Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-16
2001-01-09
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S393000, C438S655000, C438S682000
Reexamination Certificate
active
06171901
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for forming a capacitor structure for an integrated circuit, and in particular, to a process flow which features reduced oxide growth at capacitor electrode contact regions prior to the formation of silicide.
2. Description of the Related Art
It is common to incorporate passive devices in integrated circuits in mixed-signal devices. The polysilicon-to-polysilicon capacitor is a useful device due to its relatively ease of formation and its superiority in performance over a gate oxide capacitor in many applications.
FIG. 1
shows a cross-sectional view of a conventional polysilicon-to-polysilicon capacitor structure. Capacitor
100
is formed over a field oxide region
102
of an integrated circuit. Capacitor
100
includes a heavily doped lower polysilicon electrode
104
separated from a heavily doped upper polysilicon electrode
106
by an intervening dielectric layer
108
. Both lower and upper electrodes
104
and
106
include dielectric spacer structures
110
.
Lower polysilicon electrode
104
includes a first silicide contact
112
. Upper electrode
106
includes a second silicide contact
114
. Silicide contacts
112
and
114
provide low resistance electrical pathways to electrodes
104
and
106
respectively, of capacitor
100
.
It is problematic to form silicide contacts
112
and
114
in a self-aligned fashion in conjunction with formation of silicide source/gate/drain contacts of an associated CMOS structure. This is illustrated below in conjunction with FIGS.
2
A-
2
L.
FIGS.
2
A-
2
L illustrate cross-sectional views of the conventional process flow for forming the polysilicon-to-polysilicon capacitor shown in FIG.
1
.
FIG. 2A
shows the first step of this process, wherein gate oxide layer
116
is formed over single-crystal silicon region
118
located adjacent to field oxide region
102
. Undoped gate polysilicon layer
120
is then formed over gate oxide layer
116
and field oxide region
102
.
FIG. 2B
shows patterning of capacitor implant mask
122
, followed by ion implantation of conductivity-altering dopant into exposed first region
150
of gate polysilicon layer
120
. Regions of gate polysilicon layer
120
exposed to implantation in this step will form part of the lower electrode of the capacitor device.
FIG. 2C
shows removal of the capacitor implant mask, followed by formation of a CMOS mask
124
which covers single crystal silicon region
118
. Capacitor oxide layer
108
is then formed over both doped and undoped portions of gate polysilicon layer
120
. Capacitor polysilicon layer
126
is then formed over capacitor oxide layer
108
. Capacitor polysilicon layer
126
is then heavily doped by ion implantation.
FIG. 2D
shows the capacitor anneal step, wherein the heavily-doped capacitor polysilicon layer
126
is heated in the presence of N
2
gas to promote even distribution of implanted dopant throughout capacitor polysilicon layer
126
.
FIG. 2E
shows removal of the CMOS mask, followed by formation of a capacitor poly mask
128
covering first region
150
and the portion of capacitor polysilicon layer
126
which will later form the upper electrode. Capacitor polysilicon layer
126
and capacitor oxide layer
108
in unmasked areas are then etched.
FIG. 2F
shows removal of the capacitor poly mask, followed by patterning of gate poly mask
130
over a second region
152
. Second region
152
is larger than and encompasses the first region. Gate poly mask
130
covers portions of gate polysilicon layer
120
that will form the lower electrode of the capacitor, and also covers the gate of the CMOS device. Portions of gate polysilicon layer
120
excluded from mask
130
are then etched to form lower electrode
104
of the precursor capacitor, as well as gate
132
of the precursor CMOS device. At this point in the process, lower electrode
104
includes a heavily-doped portion
104
a
and an undoped portion
104
b.
FIG. 2G
shows exposing the precursor capacitor and CMOS structures to thermally oxidizing conditions. As a result, seal oxide layer
134
a
is formed over the surface of single crystal silicon
118
, seal oxide layer
134
b
is formed over the exposed surfaces of undoped portions
104
b
of the remaining gate polysilicon, and seal oxide layer
134
c
is formed over the heavily doped surface of upper polysilicon capacitor electrode
106
.
Seal oxide layer
134
c
has significantly greater thickness than either seal oxide layer
134
a
overlying single crystal silicon
118
, or seal oxide layer
134
b
overlying the undoped portion
104
b
of lower capacitor electrode
104
. This is because increasing the dopant concentration of polysilicon results in a pronounced increase in oxidation. As discussed below, the additional thickness of seal oxide layer
134
c
poses difficulties in later forming a silicide contact with upper capacitor electrode
106
.
FIG. 2H
shows formation of lightly-doped-drain (LDD) mask
136
, followed by implantation of conductivity-altering dopant in unmasked regions to form LDD regions
138
in single-crystal silicon
118
. Also during this step, dopant is introduced into the gate polysilicon
132
and also into the formerly undoped portion
104
b
of lower electrode
104
.
FIG. 2I
shows removal of the LDD mask, followed by the formation of spacer structures
110
. Spacer structures
110
are typically produced by anisotropic etching of a conforming deposited dielectric layer.
FIG. 2J
shows patterning of source/drain mask
138
, followed by implantation of high doses of conductivity altering dopant into unmasked regions to form source/drain
140
and gate
132
of CMOS device
142
. Also during the step, additional dopant is again introduced into formerly undoped portion
104
b
of lower electrode
104
, raising the doping of portion
104
b
to approximately that of doped portion
104
a.
FIG. 2K
shows the removal of seal oxide layers
134
a
,
134
b
, and
134
c
in preparation for forming silicided contacts with the upper and lower electrodes of the capacitor structure, and also with the source, gate, and drain of the CMOS device. Seal oxide layers
134
a
,
134
b
, and
134
are removed with HF etchants.
FIG. 2L
shows the formation of silicide contacts with the capacitor and CMOS device. Specifically, a silicide mask (not shown) is patterned which exposes the surface of the upper and lower capacitor electrodes, as well as the surface of the source, gate, and drain of the CMOS device. A layer of refractory metal is formed over these exposed surfaces. The metal/silicon combination is then alloyed to produce silicide contacts
114
and
112
over upper and lower electrodes
106
and
104
of capacitor
100
, as well as silicide contacts
144
over the source
140
, gate
132
, and drain
140
of CMOS device
142
. This step completes the conventional front-end process flow for the polysilicon-to-polysilicon capacitor structure.
It is critical for polysilicon-to-polysilicon capacitors to have heavily doped electrodes. Unfortunately, however, heavily doped polysilicon oxidizes to a thickness of up to 4 times that of undoped polysilicon. Because of this, the process described above in FIGS.
2
A-
2
L suffers from one serious disadvantage during formation of silicided contacts to the capacitor.
As described in connection with
FIG. 2G
, the elevated rate of oxidation of heavily doped polysilicon produces an especially thick seal oxide layer over the upper capacitor electrode. In order to remove this thick oxide layer prior to the formation of silicide contacts, extended exposure to HF etchants is required. This prolonged etchant exposure can lead to degradation of the delicate spacer structures, possibly destroying the capacitor and/or CMOS device. This is graphically illustrated in
FIG. 2K
, wherein the prolonged exposure to HF etchant required to remove seal oxide layer
134
c
has partially eroded spacers
110
.
Therefore, there is a need in the art for a process for forming a capacitor structure whic
Blair Christopher S.
Chen Weidong
Limbach & Limbach LLP
National Semiconductor Corporation
Tsai Jey
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