Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-10-09
1999-09-14
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438655, 438664, H01L 21336
Patent
active
059536144
ABSTRACT:
A process is described for forming self-aligned contacts to an MOS device on an integrated circuit structure characterized by the simultaneous formation of the metal silicide gate portion and the metal silicide source/drain portions. The process comprises forming a gate oxide layer on a silicon substrate, forming a polysilicon gate electrode layer over the gate oxide layer, and forming a layer of a first insulation material over the polysilicon gate electrode layer. Metal silicide is simultaneously formed on the exposed surface of the polysilicon gate electrode and over the exposed portions of the silicon substrate. Source/drain regions are formed in the silicon substrate, either before or after formation of the metal silicide over the exposed portions of the silicon substrate, whereby the metal silicide portions on the substrate above the source/drain regions are in electrical communication with the source/drain regions.
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Castagnetti Ruggero
Giust Gary K.
Liu Yauh-Ching
Ramesh Subramanian
Chaudhari Chandra
LSI Logic Corporation
Taylor John P.
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