Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-26
2001-04-10
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000, C257S407000, C148SDIG005
Reexamination Certificate
active
06214681
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an integrated circuit (IC) and the fabrication of an integrated circuit. More particularly, the present invention relates to an integrated circuit having polysilicon and germanium gate stacks or polysilicon and germanium thin films.
BACKGROUND OF THE INVENTION
Ultra-large scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million transistors on a substrate. The transistors are generally metal oxide semiconductor field effect transistors (MOSFETs) which include a gate conductor disposed between a source region and a drain region. The transistors can be N-channel MOSFETs or P-channel MOSFETs. The gate conductor is provided over a thin gate oxide material.
Polysilicon and germanium material and amorphous silicon and germanium material can be used in a myriad of potential semiconductor fabrication applications. For example, the gate conductor or electrode can be a polysilicon/germanium (Si
x
Ge
(
1
-x)
) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. Polysilicon/germanium gate materials are heavily doped (e.g., P+ or N+) to increase their conductivity.
A polysilicon/germanium gate conductor offers several advantages over conventional gate conductors. First, polysilicon/germanium gate conductors require a relatively low temperature rapid thermal anneal (RTA) to activate dopants (e.g., Boron (B), Phosphorous (P), etc.) in the gate conductor. A low temperature RTA facilitates the formation of ultra-shallow source/drain junctions and the formation of ultra-tight pocket regions. Second, polysilicon/germanium gate conductors effectively suppress boron penetration into a gate conductor heavily doped with phosphorous (P+). Third, polysilicon/germanium gate conductors can be utilized to adjust the threshold voltage of the transistor. The work function of a transistor is related to the concentration of germanium in the polysilicon/germanium gate conductor. This aspect is particularly advantageous in integrated circuits having transistors with several threshold voltage levels.
Germanium in the polysilicon/germanium material or amorphous silicon/germanium material can easily diffuse to the top surface of the gate conductor (stack). Germanium at the top surface can become oxidized at room temperature. Germanium diffusion to the top surface (germanium migration) is a particular problem at high concentrations (e.g., 10-50%, atomic percentage of germanium). Oxidized germanium (germanium dioxide (GeO
2
)) is easily dissolved in water and can become permanently removed from the gate structure. The loss of germanium from the gate conductor is referred to as “germanium outgassing.”
In conventional semiconductor fabrication processes, germanium outgassing can occur in at least two different situations. First, germanium outgassing can occur immediately after the polysilicon/germanium material or amorphous silicon/germanium material is provided by chemical vapor deposition (CVD). The polysilicon/germanium material or amorphous silicon/germanium material is often deposited as a thin film. The germanium exits a top surface of the thin film after deposition.
Second, germanium outgassing can occur after the gate conductor is patterned (the thin film is etched to form lines) and before conventional silicon dioxide (S
1
O
2
) or silicon nitride (Si
3
N
4
) spacers are formed. Wherever germanium outgassing occurs, it can negatively impact the formation of polysilicon/germanium or amorphous silicon/germanium thin films.
Thus, there is a need for a process which can manufacture a polysilicon/germanium or amorphous silicon/germanium thin films without significant germanium outgassing. Further still, there is a need for a polysilicon/germanium gate conductor or stack which can be formed with minimal germanium outgassing. Even further still, there is a need for a polysilicon/germanium or amorphous silicon/germanium thin film that can be efficiently manufactured.
SUMMARY OF THE INVENTION
An exemplary embodiment is related to a method of manufacturing an integrated circuit. The method includes providing a semiconductor and germanium thin film above the top surface of a substrate utilizing a semiconductor source and a germanium source, and reducing the germanium source while providing the semiconductor and germanium thin film to form a semiconductor buffer layer above the semiconductor and germanium thin film. The method also includes oxidizing at least a portion of the buffer layer and providing nitride spacers on side walls of the thin film.
Another exemplary embodiment relates to a method of manufacturing a silicon and germanium thin film. The method includes steps of: depositing a germanium and silicon material utilizing a silicon source and a germanium source, turning the germanium source off to form a silicon buffer layer over germanium and silicon material, and heating the silicon buffer layer to form an oxide layer above the silicon buffer layer.
Yet another exemplary embodiment relates to a method of providing a polysilicon and germanium thin film for a integrated circuit. The method includes providing a silicon and germanium layer above a substrate, and providing a silicon buffer layer above the silicon and germanium layer. The method also includes oxidizing the silicon layer to form a silicon oxide layer above the silicon buffer layer.
Still another embodiment relates to a transistor including a source, a drain, and a gate stack. The gate stack is disposed between the source and the drain. The gate stack includes a doped polysilicon/germanium material, a silicon buffer layer above the doped polysilicon/germanium layer, and a nitride spacer abutting lateral sides of the polysilicon/germanium material.
Advanced Micro Devices , Inc.
Foley & Lardner
Pham Long
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