Process for forming physical gate length dependent implanted reg

Details Process for forming physical gate length dependent implanted reg Process for forming physical gate length dependent implanted reg

1999-03-17

1999-11-09

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438301, 438305, H01L 21336

Patent

active

059813466

ABSTRACT:
Process for forming physical gate length dependent implanted regions in a semiconductor substrate. The process includes steps of first providing a semiconductor substrate (e.g. a silicon wafer) with a gate oxide layer on its surface, followed by the formation of a polysilicon gate layer on the gate oxide layer. An additional oxide layer is subsequently formed on the polysilicon gate layer. The resulting oxide/polysilicon stack is then patterned to form a patterned oxide/polysilicon stack layer that includes a patterned additional oxide layer and a patterned polysilicon gate layer. Next, a conformal silicon nitride layer is formed over the patterned oxide/polysilicon stack layer. The conformal silicon nitride layer is then etched (e.g. by an anisotropic etch) to form silicon nitride spacers on the sidewalls of the patterned oxide/polysilicon stack layer. After removal of the patterned additional oxide layer to leave the silicon nitride spacers extending above the patterned polysilicon gate layer, an additional polysilicon layer is deposited. The additional polysilicon layer is then etched (e.g. by an anisotropic plasma etch) to create dual (i.e. internal and external) polysilicon spacers on the sidewalls of the silicon nitride spacers. Next, dopant atoms (e.g. dopant atoms chosen to serve as a physical gate length dependent V.sub.T adjust implant) are implanted, through the patterned polysilicon gate layer, into the semiconductor substrate to create an implanted region while using the dual polysilicon spacers (the pitch and profile of their internal portions being dependent on the physical gate length) as an implant mask.

REFERENCES:
patent: 4536944 (1985-08-01), Bracco et al.
patent: 4975385 (1990-12-01), Beinglass et al.
patent: 5063172 (1991-11-01), Manley
patent: 5066606 (1991-11-01), Lee
patent: 5212106 (1993-05-01), Erb et al.
patent: 5215937 (1993-06-01), Erb et al.
patent: 5238859 (1993-08-01), Kamijo et al.
patent: 5376578 (1994-12-01), Hsu et al.
patent: 5496750 (1996-03-01), Moslehi
patent: 5514609 (1996-05-01), Chen et al.
patent: 5583061 (1996-12-01), Williams et al.
patent: 5618743 (1997-04-01), Williams et al.
patent: 5770506 (1998-06-01), Koh
Silicon Processing for the VLSI Era, vol. I: Process Technology, pp. 185, 280-283, 522, Lattice Press (1986).
Silicon Processing for the VLSI Era, vol. II: Process Integration, p. 325, Lattice Press (1990).
Silicon Processing for the VLSI Era, vol. III: The Submicron Mosfet, pp. 183-187, 226, 232-240, Lattice Press (1995).

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