Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-10
2001-05-29
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06238981
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to an improved process for forming MOS-gated devices having self-aligned trenches.
BACKGROUND OF THE INVENTION
An MOS transistor that includes a trench gate structure offers important advantages over a planar transistor for high current, low voltage switching applications. In the latter configuration, constriction occurs at high current flows, an effect that places substantial constraints on the design of a transistor intended for operation under such conditions.
A trench gate of a DMOS device typically includes a trench extending from the source to the drain and having sidewalls and a floor that are each lined with a layer of thermally grown silicon dioxide. The lined trench is filled with doped polysilicon. The structure of the trench gate allows less constricted current flow and, consequently, provides lower values of specific on-resistance. Furthermore, the trench gate makes possible a decreased cell pitch in an MOS channel extending along the vertical sidewalls of the trench from the bottom of the source across the body of the transistor to the drain below. Channel density is thereby increased, which reduces the contribution of the channel to on-resistance. The structure and performance of trench DMOS transistors are discussed in Bulucea and Rossen, “Trench DMOS Transistor Technology for High-Current (100 A Range) Switching,” in
Solid-State Electronics,
1991, Vol. 34, No. 5, pp 493-507, the disclosure of which is incorporated herein by reference. In addition to their utility in DMOS devices, trench gates are also advantageously employed in insulated gate bipolar transistors (IGBTs), MOS-controlled thyristors (MCTs), and other MOS-gated devices.
Self-aligned trenches in an MOS device allow the distance between source and trench gate contacts to be substantially reduced, enabling a beneficial increase in packing density for VLSI fabrication. U.S. Pat. No. 5,393,704 to Huang et al., the disclosure of which is incorporated herein by reference, describes a method of forming in and on a substrate a self-aligned trench contact for a device region that includes gate electrodes on the semiconductor substrate, source/drain regions within the substrate, and spacers on the gate electrode sidewalls. The sidewall spacers are used as a mask to provide an opening to the substrate where the trench contact is to be formed.
U.S. Pat. No. 5,716,886 to Wen, the disclosure of which is incorporated herein by reference, describes a method of fabricating a high-voltage MOS device in which a silicon nitride layer is used as a mask to form trench type source/drain regions in a substrate. The trench source/drain regions contain two conductive layers; portions of the same two conductive layers are included in a gate on the substrate surface.
U.S. Pat. No. 5,665,619 to Kwan et al., the disclosure of which is incorporated herein by reference, describes a method of fabricating a DMOS transistor having self-aligned contact trenches that are etched through a masked oxide
itride/oxide (ONO) sandwich on a silicon substrate. Gate polysilicon is deposited in the trenches and planarized with the nitride layer. The planarized polysilicon is covered with oxide; doping and four additional photolithographic masking steps are employed to form N+ source regions adjacent to the trenches and a P+ body ohmic content region between the source regions.
There is a continuing need for facilitating the fabrication of MOS-gated devices by a simplified process requiring fewer masking steps than are currently used. The present invention meets this need.
SUMMARY OF THE INVENTION
The present invention is directed to a process for forming an MOS-gated device having self-aligned trenches. A screen oxide layer is formed on an upper layer of a semiconductor substrate, and a nitride layer is formed on the screen oxide layer. Using a well mask, the nitride layer is patterned and etched to define a well region in the upper layer, and ions of a first conductivity type are diffused into the masked upper layer to form the well region.
Ions of a second, opposite conductivity type are implanted into the well region of the masked upper layer to form a source region extending to a selected depth that defines a source-well junction. The well mask is removed, exposing the portion of the nitride layer previously underlying the mask. An oxide insulating layer providing a hard mask is formed overlying the well and source regions in the upper layer. The remaining portions of the nitride layer and the screen oxide layer underlying it, which had been protected by the well mask, are removed, thereby exposing the portion of the substrate not masked by the oxide insulating layer.
The portion of the substrate thus exposed is etched to form a gate trench extending through the substrate to a selected depth beneath the well region. Sidewalls and a floor of an insulator are formed in the gate trench, which is filled with a semiconductor. The semiconductor material in the trench is planarized to be substantially coplanar with the upper surface of the oxide insulating layer. An interlevel dielectric layer is formed on the planarized gate trench semiconductor material and the upper surface of the oxide insulating layer. Following formation of a contact window mask on the interlevel dielectric layer, it and the underlying oxide insulating layer are etched to form contact openings to gate semiconductor material and the source region.
The gate semiconductor material and the source region are simultaneously etched through the contact openings, the source region being etched to a depth substantially corresponding to the depth of the source-well junction. Ions of the first conductivity type are implanted through the contact openings into the gate semiconductor material and the source region. The contact window mask is removed, and metal is deposited on the interlevel dielectric layer and in the contact openings, then patterned to form discrete source and gate connectors.
REFERENCES:
patent: 4767722 (1988-08-01), Blanchard
patent: 4983535 (1991-01-01), Blanchard
patent: 5082795 (1992-01-01), Temple
patent: 5100823 (1992-03-01), Yamada
patent: 5316959 (1994-05-01), Kwan et al.
patent: 5393704 (1995-02-01), Huang et al.
patent: 5567634 (1996-10-01), Hebert et al.
patent: 5665619 (1997-09-01), Kwan et al.
patent: 5684319 (1997-11-01), Hebert
patent: 5716886 (1998-02-01), Wen
patent: 5726463 (1998-03-01), Brown et al.
patent: 5891776 (1999-04-01), Han et al.
patent: 5940689 (1999-08-01), Rexer et al.
Chaudhuri Olik
Intersil Corporation
Jaeckle Fleischmann & Mugel LLP
Rao Shrinivas H.
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